2 * Ethernet specific code for CompuLab CL-SOM-AM57x module
4 * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
6 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/sys_proto.h>
16 #include "../common/eeprom.h"
18 static void cpsw_control(int enabled
)
20 /* VTP can be added here */
23 static struct cpsw_slave_data cl_som_am57x_cpsw_slaves
[] = {
25 .slave_reg_ofs
= 0x208,
26 .sliver_reg_ofs
= 0xd80,
28 .phy_if
= PHY_INTERFACE_MODE_RMII
,
31 .slave_reg_ofs
= 0x308,
32 .sliver_reg_ofs
= 0xdc0,
34 .phy_if
= PHY_INTERFACE_MODE_RMII
,
39 static struct cpsw_platform_data cl_som_am57_cpsw_data
= {
40 .mdio_base
= CPSW_MDIO_BASE
,
41 .cpsw_base
= CPSW_BASE
,
44 .cpdma_reg_ofs
= 0x800,
46 .slave_data
= cl_som_am57x_cpsw_slaves
,
49 .host_port_reg_ofs
= 0x108,
50 .hw_stats_reg_ofs
= 0x900,
52 .mac_control
= (1 << 5),
53 .control
= cpsw_control
,
55 .version
= CPSW_CTRL_VERSION_2
,
59 * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address.
60 * The information is retrieved from the SOC's registers.
62 * @port_num: port number.
64 static void cl_som_am57x_efuse_read_mac_addr(uchar
*buff
, uint port_num
)
66 uint32_t mac_hi
, mac_lo
;
69 mac_lo
= readl((*ctrl
)->control_core_mac_id_1_lo
);
70 mac_hi
= readl((*ctrl
)->control_core_mac_id_1_hi
);
72 mac_lo
= readl((*ctrl
)->control_core_mac_id_0_lo
);
73 mac_hi
= readl((*ctrl
)->control_core_mac_id_0_hi
);
76 buff
[0] = (mac_hi
& 0xFF0000) >> 16;
77 buff
[1] = (mac_hi
& 0xFF00) >> 8;
78 buff
[2] = mac_hi
& 0xFF;
79 buff
[3] = (mac_lo
& 0xFF0000) >> 16;
80 buff
[4] = (mac_lo
& 0xFF00) >> 8;
81 buff
[5] = mac_lo
& 0xFF;
85 * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot
87 * The address is retrieved retrieved from an EEPROM field or from the
89 * @env_name: U-Boot environment name.
90 * @field_name: EEPROM field name.
91 * @port_num: SOC's port number.
93 static int cl_som_am57x_handle_mac_address(char *env_name
, uint port_num
)
98 ret
= eth_env_get_enetaddr(env_name
, enetaddr
);
102 ret
= cl_eeprom_read_mac_addr(enetaddr
, CONFIG_SYS_I2C_EEPROM_BUS
);
104 if (ret
|| !is_valid_ethaddr(enetaddr
))
105 cl_som_am57x_efuse_read_mac_addr(enetaddr
, port_num
);
107 if (!is_valid_ethaddr(enetaddr
))
110 ret
= eth_env_set_enetaddr(env_name
, enetaddr
);
112 printf("cl-som-am57x: Failed to set Eth port %d MAC address\n",
118 #define CL_SOM_AM57X_PHY_ADDR2 0x01
119 #define AR8033_PHY_DEBUG_ADDR_REG 0x1d
120 #define AR8033_PHY_DEBUG_DATA_REG 0x1e
121 #define AR8033_DEBUG_RGMII_RX_CLK_DLY_REG 0x00
122 #define AR8033_DEBUG_RGMII_TX_CLK_DLY_REG 0x05
123 #define AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK (1 << 15)
124 #define AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK (1 << 8)
127 * cl_som_am57x_rgmii_clk_delay() - Set RGMII clock delay.
128 * Enable RX delay, disable TX delay.
130 static void cl_som_am57x_rgmii_clk_delay(void)
132 uint16_t mii_reg_val
;
135 devname
= miiphy_get_current_dev();
137 miiphy_write(devname
, CL_SOM_AM57X_PHY_ADDR2
, AR8033_PHY_DEBUG_ADDR_REG
,
138 AR8033_DEBUG_RGMII_RX_CLK_DLY_REG
);
139 miiphy_read(devname
, CL_SOM_AM57X_PHY_ADDR2
, AR8033_PHY_DEBUG_DATA_REG
,
141 mii_reg_val
|= AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK
;
142 miiphy_write(devname
, CL_SOM_AM57X_PHY_ADDR2
, AR8033_PHY_DEBUG_DATA_REG
,
145 miiphy_write(devname
, CL_SOM_AM57X_PHY_ADDR2
, AR8033_PHY_DEBUG_ADDR_REG
,
146 AR8033_DEBUG_RGMII_TX_CLK_DLY_REG
);
147 miiphy_read(devname
, CL_SOM_AM57X_PHY_ADDR2
, AR8033_PHY_DEBUG_DATA_REG
,
149 mii_reg_val
&= ~AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK
;
150 miiphy_write(devname
, CL_SOM_AM57X_PHY_ADDR2
, AR8033_PHY_DEBUG_DATA_REG
,
154 #define CL_SOM_AM57X_GPIO_PHY1_RST 92 /* GPIO3_28 */
155 #define CL_SOM_AM57X_RGMII_PORT1 1
157 int board_eth_init(bd_t
*bis
)
161 char *cpsw_phy_envval
;
162 int cpsw_act_phy
= 1;
164 /* SB-SOM-AM57x primary Eth (P21) is routed to RGMII1 */
165 ret
= cl_som_am57x_handle_mac_address("ethaddr",
166 CL_SOM_AM57X_RGMII_PORT1
);
171 /* Select RGMII for GMII1_SEL */
172 ctrl_val
= readl((*ctrl
)->control_core_control_io1
) & (~0x33);
174 writel(ctrl_val
, (*ctrl
)->control_core_control_io1
);
177 gpio_request(CL_SOM_AM57X_GPIO_PHY1_RST
, "phy1_rst");
178 gpio_direction_output(CL_SOM_AM57X_GPIO_PHY1_RST
, 0);
181 gpio_set_value(CL_SOM_AM57X_GPIO_PHY1_RST
, 1);
184 cpsw_phy_envval
= env_get("cpsw_phy");
185 if (cpsw_phy_envval
!= NULL
)
186 cpsw_act_phy
= simple_strtoul(cpsw_phy_envval
, NULL
, 0);
188 cl_som_am57_cpsw_data
.active_slave
= cpsw_act_phy
;
190 ret
= cpsw_register(&cl_som_am57_cpsw_data
);
192 printf("Error %d registering CPSW switch\n", ret
);
194 /* Set RGMII clock delay */
195 cl_som_am57x_rgmii_clk_delay();