2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Based on mx6qsabrelite.c file
4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5 * Leo Sartre, <lsartre@adeneo-embedded.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/sata.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/mxc_i2c.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h>
25 #include <fsl_esdhc.h>
27 #include <power/pmic.h>
28 #include <power/pfuze100_pmic.h>
30 #include <ipu_pixfmt.h>
35 #include <spi_flash.h>
38 DECLARE_GLOBAL_DATA_PTR
;
40 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
41 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
53 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
55 #define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
58 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
59 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
64 gd
->ram_size
= imx_ddr_size();
69 static iomux_v3_cfg_t
const uart2_pads
[] = {
70 IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
71 IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
74 static iomux_v3_cfg_t
const usdhc2_pads
[] = {
75 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
76 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
77 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
78 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
79 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
80 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
81 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
84 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
85 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
86 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
87 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
88 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
89 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
90 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
91 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
92 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
93 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
94 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
95 IOMUX_PADS(PAD_SD3_RST__SD3_RESET
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
98 static iomux_v3_cfg_t
const usdhc4_pads
[] = {
99 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
100 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
101 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
102 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
103 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
104 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
105 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
106 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
107 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
108 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
109 IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
112 static iomux_v3_cfg_t
const usb_otg_pads
[] = {
113 IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
114 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
117 static iomux_v3_cfg_t enet_pads_ksz9031
[] = {
118 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
119 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
120 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
121 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
122 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
123 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
124 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
125 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
126 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
127 IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
128 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
129 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
130 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
131 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
132 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
135 static iomux_v3_cfg_t enet_pads_final_ksz9031
[] = {
136 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
137 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
138 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
139 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
140 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
141 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
144 static iomux_v3_cfg_t enet_pads_ar8035
[] = {
145 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
146 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
147 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
148 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
149 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
150 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
151 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
152 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
153 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
154 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
155 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
156 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
157 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
158 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
159 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
162 static iomux_v3_cfg_t
const ecspi1_pads
[] = {
163 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
164 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
165 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
166 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
169 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
170 struct i2c_pads_info mx6q_i2c_pad_info1
= {
172 .i2c_mode
= MX6Q_PAD_KEY_COL3__I2C2_SCL
| PC
,
173 .gpio_mode
= MX6Q_PAD_KEY_COL3__GPIO4_IO12
| PC
,
174 .gp
= IMX_GPIO_NR(4, 12)
177 .i2c_mode
= MX6Q_PAD_KEY_ROW3__I2C2_SDA
| PC
,
178 .gpio_mode
= MX6Q_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
179 .gp
= IMX_GPIO_NR(4, 13)
183 struct i2c_pads_info mx6dl_i2c_pad_info1
= {
185 .i2c_mode
= MX6DL_PAD_KEY_COL3__I2C2_SCL
| PC
,
186 .gpio_mode
= MX6DL_PAD_KEY_COL3__GPIO4_IO12
| PC
,
187 .gp
= IMX_GPIO_NR(4, 12)
190 .i2c_mode
= MX6DL_PAD_KEY_ROW3__I2C2_SDA
| PC
,
191 .gpio_mode
= MX6DL_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
192 .gp
= IMX_GPIO_NR(4, 13)
196 #define I2C_PMIC 1 /* I2C2 port is used to connect to the PMIC */
198 struct interface_level
{
203 static struct interface_level mipi_levels
[] = {
208 /* setup board specific PMIC */
209 int power_init_board(void)
216 /* configure I2C multiplexer */
217 gpio_direction_output(MX6Q_QMX6_PFUZE_MUX
, 1);
219 power_pfuze100_init(I2C_PMIC
);
220 p
= pmic_get("PFUZE100");
228 pmic_reg_read(p
, PFUZE100_DEVICEID
, &id1
);
229 pmic_reg_read(p
, PFUZE100_REVID
, &id2
);
230 printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1
, id2
);
235 /* set level of MIPI if specified */
236 lv_mipi
= getenv("lv_mipi");
240 for (i
= 0; i
< ARRAY_SIZE(mipi_levels
); i
++) {
241 if (!strcmp(mipi_levels
[i
].name
, lv_mipi
)) {
242 printf("set MIPI level %s\n", mipi_levels
[i
].name
);
243 ret
= pmic_reg_write(p
, PFUZE100_VGEN4VOL
,
244 mipi_levels
[i
].value
);
253 int board_eth_init(bd_t
*bis
)
255 struct phy_device
*phydev
;
257 unsigned short id1
, id2
;
260 /* check whether KSZ9031 or AR8035 has to be configured */
261 SETUP_IOMUX_PADS(enet_pads_ar8035
);
264 gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
266 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
269 bus
= fec_get_miibus(IMX_FEC_BASE
, -1);
272 phydev
= phy_find_by_mask(bus
, (0xf << 4), PHY_INTERFACE_MODE_RGMII
);
274 printf("Error: phy device not found.\n");
280 id1
= phy_read(phydev
, MDIO_DEVAD_NONE
, 2);
281 id2
= phy_read(phydev
, MDIO_DEVAD_NONE
, 3);
283 if ((id1
== 0x22) && ((id2
& 0xFFF0) == 0x1620)) {
284 /* re-configure for Micrel KSZ9031 */
285 printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
288 /* phy reset: gpio3-23 */
289 gpio_set_value(IMX_GPIO_NR(3, 23), 0);
290 gpio_set_value(IMX_GPIO_NR(6, 30), (phydev
->addr
>> 2));
291 gpio_set_value(IMX_GPIO_NR(6, 25), 1);
292 gpio_set_value(IMX_GPIO_NR(6, 27), 1);
293 gpio_set_value(IMX_GPIO_NR(6, 28), 1);
294 gpio_set_value(IMX_GPIO_NR(6, 29), 1);
295 SETUP_IOMUX_PADS(enet_pads_ksz9031
);
296 gpio_set_value(IMX_GPIO_NR(6, 24), 1);
298 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
299 SETUP_IOMUX_PADS(enet_pads_final_ksz9031
);
300 } else if ((id1
== 0x004d) && (id2
== 0xd072)) {
301 /* configure Atheros AR8035 - actually nothing to do */
302 printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
305 printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1
, id2
);
310 ret
= fec_probe(bis
, -1, IMX_FEC_BASE
, bus
, phydev
);
323 int mx6_rgmii_rework(struct phy_device
*phydev
)
325 unsigned short id1
, id2
;
328 /* check whether KSZ9031 or AR8035 has to be configured */
329 id1
= phy_read(phydev
, MDIO_DEVAD_NONE
, 2);
330 id2
= phy_read(phydev
, MDIO_DEVAD_NONE
, 3);
332 if ((id1
== 0x22) && ((id2
& 0xFFF0) == 0x1620)) {
333 /* finalize phy configuration for Micrel KSZ9031 */
334 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, 2);
335 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 4);
336 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, MII_KSZ9031_MOD_DATA_POST_INC_W
| 0x2);
337 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 0x0000);
339 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, 2);
340 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 5);
341 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, MII_KSZ9031_MOD_DATA_POST_INC_W
| 0x2);
342 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, MII_KSZ9031_MOD_REG
);
344 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, 2);
345 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 6);
346 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, MII_KSZ9031_MOD_DATA_POST_INC_W
| 0x2);
347 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 0xFFFF);
349 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, 2);
350 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 8);
351 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, MII_KSZ9031_MOD_DATA_POST_INC_W
| 0x2);
352 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 0x3FFF);
354 /* fix KSZ9031 link up issue */
355 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, 0x0);
356 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 0x4);
357 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, MII_KSZ9031_MOD_DATA_NO_POST_INC
);
358 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 0x6);
359 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, MII_KSZ9031_MOD_REG
);
360 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 0x3);
361 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, MII_KSZ9031_MOD_DATA_NO_POST_INC
);
362 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, 0x1A80);
365 if ((id1
== 0x004d) && (id2
== 0xd072)) {
366 /* enable AR8035 ouput a 125MHz clk from CLK_25M */
367 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, 0x7);
368 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, MII_KSZ9031_MOD_DATA_POST_INC_RW
| 0x16);
369 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_CONTROL
, MII_KSZ9031_MOD_DATA_NO_POST_INC
| 0x7);
370 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
);
373 phy_write(phydev
, MDIO_DEVAD_NONE
, MMD_ACCESS_REG_DATA
, val
);
375 /* introduce tx clock delay */
376 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x5);
377 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0x1e);
379 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, val
);
381 /* disable hibernation */
382 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0xb);
383 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0x1e);
384 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x3c40);
389 int board_phy_config(struct phy_device
*phydev
)
391 mx6_rgmii_rework(phydev
);
393 if (phydev
->drv
->config
)
394 phydev
->drv
->config(phydev
);
399 static void setup_iomux_uart(void)
401 SETUP_IOMUX_PADS(uart2_pads
);
404 #ifdef CONFIG_MXC_SPI
405 static void setup_spi(void)
407 imx_iomux_v3_setup_multiple_pads(ecspi1_pads
, ARRAY_SIZE(ecspi1_pads
));
408 gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
412 #ifdef CONFIG_FSL_ESDHC
413 static struct fsl_esdhc_cfg usdhc_cfg
[] = {
419 int board_mmc_getcd(struct mmc
*mmc
)
421 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
424 switch (cfg
->esdhc_base
) {
425 case USDHC2_BASE_ADDR
:
426 gpio_direction_input(IMX_GPIO_NR(1, 4));
427 ret
= !gpio_get_value(IMX_GPIO_NR(1, 4));
429 case USDHC3_BASE_ADDR
:
430 ret
= 1; /* eMMC is always present */
432 case USDHC4_BASE_ADDR
:
433 gpio_direction_input(IMX_GPIO_NR(2, 6));
434 ret
= !gpio_get_value(IMX_GPIO_NR(2, 6));
437 printf("Bad USDHC interface\n");
443 int board_mmc_init(bd_t
*bis
)
445 #ifndef CONFIG_SPL_BUILD
449 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
450 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
451 usdhc_cfg
[2].sdhc_clk
= mxc_get_clock(MXC_ESDHC4_CLK
);
453 SETUP_IOMUX_PADS(usdhc2_pads
);
454 SETUP_IOMUX_PADS(usdhc3_pads
);
455 SETUP_IOMUX_PADS(usdhc4_pads
);
457 for (i
= 0; i
< ARRAY_SIZE(usdhc_cfg
); i
++) {
458 status
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
465 SETUP_IOMUX_PADS(usdhc4_pads
);
466 usdhc_cfg
[0].esdhc_base
= USDHC4_BASE_ADDR
;
467 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC4_CLK
);
468 gd
->arch
.sdhc_clk
= usdhc_cfg
[0].sdhc_clk
;
470 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[0]);
475 int board_ehci_hcd_init(int port
)
479 SETUP_IOMUX_PADS(usb_otg_pads
);
481 * set daisy chain for otg_pin_id on 6q.
482 * for 6dl, this bit is reserved
484 imx_iomux_set_gpr_register(1, 13, 1, 1);
490 printf("Invalid USB port: %d\n", port
);
497 int board_ehci_power(int port
, int on
)
503 gpio_direction_output(IMX_GPIO_NR(5, 5), on
);
506 printf("Invalid USB port: %d\n", port
);
513 struct display_info_t
{
517 int (*detect
)(struct display_info_t
const *dev
);
518 void (*enable
)(struct display_info_t
const *dev
);
519 struct fb_videomode mode
;
522 static void disable_lvds(struct display_info_t
const *dev
)
524 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
526 clrbits_le32(&iomux
->gpr
[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK
|
527 IOMUXC_GPR2_LVDS_CH1_MODE_MASK
);
530 static void do_enable_hdmi(struct display_info_t
const *dev
)
533 imx_enable_hdmi_phy();
536 static struct display_info_t
const displays
[] = {
540 .pixfmt
= IPU_PIX_FMT_RGB666
,
557 .vmode
= FB_VMODE_NONINTERLACED
} },
561 .pixfmt
= IPU_PIX_FMT_RGB24
,
563 .enable
= do_enable_hdmi
,
577 .vmode
= FB_VMODE_NONINTERLACED
} }
580 int board_video_skip(void)
584 char const *panel
= getenv("panel");
586 for (i
= 0; i
< ARRAY_SIZE(displays
); i
++) {
587 struct display_info_t
const *dev
= displays
+ i
;
588 if (dev
->detect
&& dev
->detect(dev
)) {
589 panel
= dev
->mode
.name
;
590 printf("auto-detected panel %s\n", panel
);
595 panel
= displays
[0].mode
.name
;
596 printf("No panel detected: default to %s\n", panel
);
600 for (i
= 0; i
< ARRAY_SIZE(displays
); i
++) {
601 if (!strcmp(panel
, displays
[i
].mode
.name
))
605 if (i
< ARRAY_SIZE(displays
)) {
606 ret
= ipuv3_fb_init(&displays
[i
].mode
, 0, displays
[i
].pixfmt
);
608 if (displays
[i
].enable
)
609 displays
[i
].enable(displays
+ i
);
610 printf("Display: %s (%ux%u)\n",
611 displays
[i
].mode
.name
, displays
[i
].mode
.xres
,
612 displays
[i
].mode
.yres
);
614 printf("LCD %s cannot be configured: %d\n",
615 displays
[i
].mode
.name
, ret
);
617 printf("unsupported panel %s\n", panel
);
624 static void setup_display(void)
626 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
627 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
633 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
634 setbits_le32(&mxc_ccm
->CCGR3
, MXC_CCM_CCGR3_LDB_DI0_MASK
|
635 MXC_CCM_CCGR3_LDB_DI1_MASK
);
637 /* set LDB0, LDB1 clk select to 011/011 */
638 reg
= readl(&mxc_ccm
->cs2cdr
);
639 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
640 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
);
641 reg
|= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
) |
642 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
);
643 writel(reg
, &mxc_ccm
->cs2cdr
);
645 setbits_le32(&mxc_ccm
->cscmr2
, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV
|
646 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV
);
648 setbits_le32(&mxc_ccm
->chsccdr
, CHSCCDR_CLK_SEL_LDB_DI0
<<
649 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
|
650 CHSCCDR_CLK_SEL_LDB_DI0
<<
651 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET
);
653 reg
= IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
654 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
655 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
656 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
657 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
658 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
659 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
660 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
661 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
;
662 writel(reg
, &iomux
->gpr
[2]);
664 reg
= readl(&iomux
->gpr
[3]);
665 reg
= (reg
& ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
|
666 IOMUXC_GPR3_HDMI_MUX_CTL_MASK
)) |
667 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<
668 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET
);
669 writel(reg
, &iomux
->gpr
[3]);
673 * Do not overwrite the console
674 * Use always serial for U-Boot console
676 int overwrite_console(void)
681 static bool is_mx6q(void)
683 if (is_cpu_type(MXC_CPU_MX6Q
) || is_cpu_type(MXC_CPU_MX6D
))
689 int board_early_init_f(void)
694 #ifdef CONFIG_MXC_SPI
702 /* address of boot parameters */
703 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
707 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info1
);
709 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info1
);
711 #ifdef CONFIG_CMD_SATA
720 char *type
= "unknown";
722 if (is_cpu_type(MXC_CPU_MX6Q
))
724 else if (is_cpu_type(MXC_CPU_MX6D
))
726 else if (is_cpu_type(MXC_CPU_MX6DL
))
728 else if (is_cpu_type(MXC_CPU_MX6SOLO
))
731 printf("Board: conga-QMX6 %s\n", type
);
736 #ifdef CONFIG_MXC_SPI
737 int board_spi_cs_gpio(unsigned bus
, unsigned cs
)
739 return (bus
== 0 && cs
== 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL
;
743 #ifdef CONFIG_CMD_BMODE
744 static const struct boot_mode board_boot_modes
[] = {
745 /* 4 bit bus width */
746 {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
747 {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
752 int misc_init_r(void)
754 #ifdef CONFIG_CMD_BMODE
755 add_board_boot_modes(board_boot_modes
);
760 int board_late_init(void)
762 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
764 setenv("board_rev", "MX6Q");
766 setenv("board_rev", "MX6DL");
772 #ifdef CONFIG_SPL_BUILD
773 #include <asm/arch/mx6-ddr.h>
776 #include <spi_flash.h>
779 const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs
= {
780 .dram_sdclk_0
= 0x00000030,
781 .dram_sdclk_1
= 0x00000030,
782 .dram_cas
= 0x00000030,
783 .dram_ras
= 0x00000030,
784 .dram_reset
= 0x00000030,
785 .dram_sdcke0
= 0x00003000,
786 .dram_sdcke1
= 0x00003000,
787 .dram_sdba2
= 0x00000000,
788 .dram_sdodt0
= 0x00000030,
789 .dram_sdodt1
= 0x00000030,
790 .dram_sdqs0
= 0x00000030,
791 .dram_sdqs1
= 0x00000030,
792 .dram_sdqs2
= 0x00000030,
793 .dram_sdqs3
= 0x00000030,
794 .dram_sdqs4
= 0x00000030,
795 .dram_sdqs5
= 0x00000030,
796 .dram_sdqs6
= 0x00000030,
797 .dram_sdqs7
= 0x00000030,
798 .dram_dqm0
= 0x00000030,
799 .dram_dqm1
= 0x00000030,
800 .dram_dqm2
= 0x00000030,
801 .dram_dqm3
= 0x00000030,
802 .dram_dqm4
= 0x00000030,
803 .dram_dqm5
= 0x00000030,
804 .dram_dqm6
= 0x00000030,
805 .dram_dqm7
= 0x00000030,
808 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs
= {
809 .dram_sdclk_0
= 0x00000030,
810 .dram_sdclk_1
= 0x00000030,
811 .dram_cas
= 0x00000030,
812 .dram_ras
= 0x00000030,
813 .dram_reset
= 0x00000030,
814 .dram_sdcke0
= 0x00003000,
815 .dram_sdcke1
= 0x00003000,
816 .dram_sdba2
= 0x00000000,
817 .dram_sdodt0
= 0x00000030,
818 .dram_sdodt1
= 0x00000030,
819 .dram_sdqs0
= 0x00000030,
820 .dram_sdqs1
= 0x00000030,
821 .dram_sdqs2
= 0x00000030,
822 .dram_sdqs3
= 0x00000030,
823 .dram_sdqs4
= 0x00000030,
824 .dram_sdqs5
= 0x00000030,
825 .dram_sdqs6
= 0x00000030,
826 .dram_sdqs7
= 0x00000030,
827 .dram_dqm0
= 0x00000030,
828 .dram_dqm1
= 0x00000030,
829 .dram_dqm2
= 0x00000030,
830 .dram_dqm3
= 0x00000030,
831 .dram_dqm4
= 0x00000030,
832 .dram_dqm5
= 0x00000030,
833 .dram_dqm6
= 0x00000030,
834 .dram_dqm7
= 0x00000030,
837 const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs
= {
838 .grp_ddr_type
= 0x000C0000,
839 .grp_ddrmode_ctl
= 0x00020000,
840 .grp_ddrpke
= 0x00000000,
841 .grp_addds
= 0x00000030,
842 .grp_ctlds
= 0x00000030,
843 .grp_ddrmode
= 0x00020000,
844 .grp_b0ds
= 0x00000030,
845 .grp_b1ds
= 0x00000030,
846 .grp_b2ds
= 0x00000030,
847 .grp_b3ds
= 0x00000030,
848 .grp_b4ds
= 0x00000030,
849 .grp_b5ds
= 0x00000030,
850 .grp_b6ds
= 0x00000030,
851 .grp_b7ds
= 0x00000030,
854 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
855 .grp_ddr_type
= 0x000c0000,
856 .grp_ddrmode_ctl
= 0x00020000,
857 .grp_ddrpke
= 0x00000000,
858 .grp_addds
= 0x00000030,
859 .grp_ctlds
= 0x00000030,
860 .grp_ddrmode
= 0x00020000,
861 .grp_b0ds
= 0x00000030,
862 .grp_b1ds
= 0x00000030,
863 .grp_b2ds
= 0x00000030,
864 .grp_b3ds
= 0x00000030,
865 .grp_b4ds
= 0x00000030,
866 .grp_b5ds
= 0x00000030,
867 .grp_b6ds
= 0x00000030,
868 .grp_b7ds
= 0x00000030,
871 const struct mx6_mmdc_calibration mx6q_mmcd_calib
= {
872 .p0_mpwldectrl0
= 0x0016001A,
873 .p0_mpwldectrl1
= 0x0023001C,
874 .p1_mpwldectrl0
= 0x0028003A,
875 .p1_mpwldectrl1
= 0x001F002C,
876 .p0_mpdgctrl0
= 0x43440354,
877 .p0_mpdgctrl1
= 0x033C033C,
878 .p1_mpdgctrl0
= 0x43300368,
879 .p1_mpdgctrl1
= 0x03500330,
880 .p0_mprddlctl
= 0x3228242E,
881 .p1_mprddlctl
= 0x2C2C2636,
882 .p0_mpwrdlctl
= 0x36323A38,
883 .p1_mpwrdlctl
= 0x42324440,
886 const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib
= {
887 .p0_mpwldectrl0
= 0x00080016,
888 .p0_mpwldectrl1
= 0x001D0016,
889 .p1_mpwldectrl0
= 0x0018002C,
890 .p1_mpwldectrl1
= 0x000D001D,
891 .p0_mpdgctrl0
= 0x43200334,
892 .p0_mpdgctrl1
= 0x0320031C,
893 .p1_mpdgctrl0
= 0x0344034C,
894 .p1_mpdgctrl1
= 0x03380314,
895 .p0_mprddlctl
= 0x3E36383A,
896 .p1_mprddlctl
= 0x38363240,
897 .p0_mpwrdlctl
= 0x36364238,
898 .p1_mpwrdlctl
= 0x4230423E,
901 static const struct mx6_mmdc_calibration mx6s_mmcd_calib
= {
902 .p0_mpwldectrl0
= 0x00480049,
903 .p0_mpwldectrl1
= 0x00410044,
904 .p0_mpdgctrl0
= 0x42480248,
905 .p0_mpdgctrl1
= 0x023C023C,
906 .p0_mprddlctl
= 0x40424644,
907 .p0_mpwrdlctl
= 0x34323034,
910 const struct mx6_mmdc_calibration mx6dl_mmcd_calib
= {
911 .p0_mpwldectrl0
= 0x0043004B,
912 .p0_mpwldectrl1
= 0x003A003E,
913 .p1_mpwldectrl0
= 0x0047004F,
914 .p1_mpwldectrl1
= 0x004E0061,
915 .p0_mpdgctrl0
= 0x42500250,
916 .p0_mpdgctrl1
= 0x0238023C,
917 .p1_mpdgctrl0
= 0x42640264,
918 .p1_mpdgctrl1
= 0x02500258,
919 .p0_mprddlctl
= 0x40424846,
920 .p1_mprddlctl
= 0x46484842,
921 .p0_mpwrdlctl
= 0x38382C30,
922 .p1_mpwrdlctl
= 0x34343430,
925 static struct mx6_ddr3_cfg mem_ddr_2g
= {
938 static struct mx6_ddr3_cfg mem_ddr_4g
= {
951 static void ccgr_init(void)
953 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
955 writel(0x00C03F3F, &ccm
->CCGR0
);
956 writel(0x0030FC03, &ccm
->CCGR1
);
957 writel(0x0FFFC000, &ccm
->CCGR2
);
958 writel(0x3FF00000, &ccm
->CCGR3
);
959 writel(0x00FFF300, &ccm
->CCGR4
);
960 writel(0x0F0000C3, &ccm
->CCGR5
);
961 writel(0x000003FF, &ccm
->CCGR6
);
964 static void gpr_init(void)
966 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
968 /* enable AXI cache for VDOA/VPU/IPU */
969 writel(0xF00000CF, &iomux
->gpr
[4]);
970 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
971 writel(0x007F007F, &iomux
->gpr
[6]);
972 writel(0x007F007F, &iomux
->gpr
[7]);
975 /* Define a minimal structure so that the part number can be read via SPL */
978 /* size of checksummed part in bytes */
980 /* checksum corrected byte */
982 /* decimal serial number, packed BCD */
983 unsigned char serial
[6];
984 /* part number, right justified, ASCII */
985 unsigned char pn
[16];
988 static void conv_ascii(unsigned char *dst
, unsigned char *src
, int len
)
991 unsigned char *sptr
= src
;
992 unsigned char *dptr
= dst
;
1005 #define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
1006 static bool is_2gb(void)
1008 struct spi_flash
*spi
;
1010 char buf
[sizeof(struct mfgdata
)];
1011 struct mfgdata
*data
= (struct mfgdata
*)buf
;
1012 unsigned char outbuf
[32];
1014 spi
= spi_flash_probe(CONFIG_ENV_SPI_BUS
,
1016 CONFIG_ENV_SPI_MAX_HZ
, CONFIG_ENV_SPI_MODE
);
1017 ret
= spi_flash_read(spi
, CFG_MFG_ADDR_OFFSET
, sizeof(struct mfgdata
),
1022 /* Congatec Part Numbers 104 and 105 have 2GiB of RAM */
1023 conv_ascii(outbuf
, data
->pn
, sizeof(data
->pn
));
1024 if (!memcmp(outbuf
, "016104", 6) || !memcmp(outbuf
, "016105", 6))
1030 static void spl_dram_init(int width
)
1032 struct mx6_ddr_sysinfo sysinfo
= {
1033 /* width of data bus:0=16,1=32,2=64 */
1034 .dsize
= width
/ 32,
1035 /* config for full 4GB range so that get_mem_size() works */
1036 .cs_density
= 32, /* 32Gb per CS */
1037 /* single chip select */
1050 if (is_cpu_type(MXC_CPU_MX6Q
) && is_2gb()) {
1051 mx6dq_dram_iocfg(width
, &mx6q_ddr_ioregs
, &mx6q_grp_ioregs
);
1052 mx6_dram_cfg(&sysinfo
, &mx6q_2g_mmcd_calib
, &mem_ddr_4g
);
1057 mx6dq_dram_iocfg(width
, &mx6q_ddr_ioregs
, &mx6q_grp_ioregs
);
1058 mx6_dram_cfg(&sysinfo
, &mx6q_mmcd_calib
, &mem_ddr_2g
);
1059 } else if (is_cpu_type(MXC_CPU_MX6SOLO
)) {
1061 mx6sdl_dram_iocfg(width
, &mx6dl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
1062 mx6_dram_cfg(&sysinfo
, &mx6s_mmcd_calib
, &mem_ddr_4g
);
1063 } else if (is_cpu_type(MXC_CPU_MX6DL
)) {
1065 mx6sdl_dram_iocfg(width
, &mx6dl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
1066 mx6_dram_cfg(&sysinfo
, &mx6dl_mmcd_calib
, &mem_ddr_2g
);
1070 void board_init_f(ulong dummy
)
1072 /* setup AIPS and disable watchdog */
1078 /* iomux and setup of i2c */
1079 board_early_init_f();
1081 /* setup GP timer */
1084 /* UART clocks enabled and gd valid - init serial console */
1085 preloader_console_init();
1087 /* Needed for malloc() to work in SPL prior to board_init_r() */
1090 /* DDR initialization */
1091 if (is_cpu_type(MXC_CPU_MX6SOLO
))
1096 /* Clear the BSS. */
1097 memset(__bss_start
, 0, __bss_end
- __bss_start
);
1099 /* load/boot image from boot device */
1100 board_init_r(NULL
, 0);