board/cpu87/cpu87.c

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <ioports.h>
  10 #include <mpc8260.h>
  11 #include "cpu87.h"
  12 #include <pci.h>
  13 #include <netdev.h>
  14
  15 /*
  16  * I/O Port configuration table
  17  *
  18  * if conf is 1, then that port pin will be configured at boot time
  19  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  20  */
  21
  22 const iop_conf_t iop_conf_tab[4][32] = {
  23
  24     /* Port A configuration */
  25     {   /*            conf ppar psor pdir podr pdat */
  26         /* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
  27         /* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
  28         /* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
  29         /* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
  30         /* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
  31         /* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
  32         /* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
  33         /* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
  34         /* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
  35         /* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
  36         /* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
  37         /* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
  38         /* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
  39         /* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
  40         /* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
  41         /* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
  42         /* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
  43         /* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
  44         /* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
  45         /* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
  46         /* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
  47         /* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
  48         /* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
  49         /* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
  50         /* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
  51         /* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
  52         /* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
  53         /* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
  54         /* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
  55         /* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
  56         /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
  57         /* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
  58     },
  59
  60     /* Port B configuration */
  61     {   /*            conf ppar psor pdir podr pdat */
  62         /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  63         /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  64         /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  65         /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  66         /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  67         /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  68         /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  69         /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
  70         /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
  71         /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
  72         /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
  73         /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
  74         /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
  75         /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
  76         /* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
  77         /* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
  78         /* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
  79         /* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
  80         /* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
  81         /* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
  82         /* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
  83         /* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
  84         /* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
  85         /* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
  86         /* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
  87         /* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
  88         /* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
  89         /* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
  90         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
  91         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
  92         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
  93         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
  94     },
  95
  96     /* Port C */
  97     {   /*            conf ppar psor pdir podr pdat */
  98         /* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
  99         /* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
 100         /* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
 101         /* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
 102         /* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
 103         /* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
 104         /* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
 105         /* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
 106         /* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
 107         /* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
 108         /* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
 109         /* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
 110         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
 111         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
 112         /* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
 113         /* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
 114         /* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
 115         /* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
 116         /* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
 117         /* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
 118         /* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
 119         /* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
 120         /* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
 121         /* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
 122         /* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
 123         /* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
 124         /* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
 125         /* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
 126         /* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
 127         /* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
 128         /* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
 129         /* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
 130     },
 131
 132     /* Port D */
 133     {   /*            conf ppar psor pdir podr pdat */
 134         /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
 135         /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
 136         /* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
 137         /* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
 138         /* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
 139         /* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
 140         /* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
 141         /* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
 142         /* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
 143         /* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
 144         /* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
 145         /* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
 146         /* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
 147         /* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
 148         /* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
 149         /* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
 150 #if defined(CONFIG_SOFT_I2C)
 151         /* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
 152         /* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
 153 #else
 154 #if defined(CONFIG_HARD_I2C)
 155         /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
 156         /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
 157 #else /* normal I/O port pins */
 158         /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
 159         /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
 160 #endif
 161 #endif
 162         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 163         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 164         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 165         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 166         /* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 167         /* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 168         /* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
 169         /* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
 170         /* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
 171         /* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
 172         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
 173         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
 174         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
 175         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
 176     }
 177 };
 178
 179 /* ------------------------------------------------------------------------- */
 180
 181 /* Check Board Identity:
 182  */
 183 int checkboard (void)
 184 {
 185         printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f);
 186         return 0;
 187 }
 188
 189 /* ------------------------------------------------------------------------- */
 190
 191 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 192  *
 193  * This routine performs standard 8260 initialization sequence
 194  * and calculates the available memory size. It may be called
 195  * several times to try different SDRAM configurations on both
 196  * 60x and local buses.
 197  */
 198 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 199                           ulong orx, volatile uchar * base)
 200 {
 201         volatile uchar c = 0xff;
 202         volatile uint *sdmr_ptr;
 203         volatile uint *orx_ptr;
 204         ulong maxsize, size;
 205         int i;
 206
 207         /* We must be able to test a location outsize the maximum legal size
 208          * to find out THAT we are outside; but this address still has to be
 209          * mapped by the controller. That means, that the initial mapping has
 210          * to be (at least) twice as large as the maximum expected size.
 211          */
 212         maxsize = (1 + (~orx | 0x7fff)) / 2;
 213
 214         /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 215          * we are configuring CS1 if base != 0
 216          */
 217         sdmr_ptr = &memctl->memc_psdmr;
 218         orx_ptr = &memctl->memc_or2;
 219
 220         *orx_ptr = orx;
 221
 222         /*
 223          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 224          *
 225          * "At system reset, initialization software must set up the
 226          *  programmable parameters in the memory controller banks registers
 227          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 228          *  system software should execute the following initialization sequence
 229          *  for each SDRAM device.
 230          *
 231          *  1. Issue a PRECHARGE-ALL-BANKS command
 232          *  2. Issue eight CBR REFRESH commands
 233          *  3. Issue a MODE-SET command to initialize the mode register
 234          *
 235          *  The initial commands are executed by setting P/LSDMR[OP] and
 236          *  accessing the SDRAM with a single-byte transaction."
 237          *
 238          * The appropriate BRx/ORx registers have already been set when we
 239          * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 240          */
 241
 242         *sdmr_ptr = sdmr | PSDMR_OP_PREA;
 243         *base = c;
 244
 245         *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
 246         for (i = 0; i < 8; i++)
 247                 *base = c;
 248
 249         *sdmr_ptr = sdmr | PSDMR_OP_MRW;
 250         *(base + CONFIG_SYS_MRS_OFFS) = c;      /* setting MR on address lines */
 251
 252         *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 253         *base = c;
 254
 255         size = get_ram_size((long *)base, maxsize);
 256
 257         *orx_ptr = orx | ~(size - 1);
 258
 259         return (size);
 260 }
 261
 262 phys_size_t initdram (int board_type)
 263 {
 264         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 265         volatile memctl8260_t *memctl = &immap->im_memctl;
 266
 267 #ifndef CONFIG_SYS_RAMBOOT
 268         ulong size8, size9, size10;
 269 #endif
 270         long psize;
 271
 272         psize = 32 * 1024 * 1024;
 273
 274         memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 275         memctl->memc_psrt = CONFIG_SYS_PSRT;
 276
 277 #ifndef CONFIG_SYS_RAMBOOT
 278         /* 60x SDRAM setup:
 279          */
 280         size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
 281                           (uchar *) CONFIG_SYS_SDRAM_BASE);
 282
 283         size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
 284                           (uchar *) CONFIG_SYS_SDRAM_BASE);
 285
 286         size10 = try_init (memctl, CONFIG_SYS_PSDMR_10COL, CONFIG_SYS_OR2_10COL,
 287                           (uchar *) CONFIG_SYS_SDRAM_BASE);
 288
 289         psize = max(size8,max(size9,size10));
 290
 291         if (psize == size8) {
 292                 psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
 293                                   (uchar *) CONFIG_SYS_SDRAM_BASE);
 294                 printf ("(60x:8COL) ");
 295         } else if (psize == size9){
 296                 psize = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
 297                                   (uchar *) CONFIG_SYS_SDRAM_BASE);
 298                 printf ("(60x:9COL) ");
 299         } else
 300                 printf ("(60x:10COL) ");
 301
 302 #endif  /* CONFIG_SYS_RAMBOOT */
 303
 304         icache_enable ();
 305
 306         return (psize);
 307 }
 308
 309 #if defined(CONFIG_CMD_DOC)
 310 void doc_init (void)
 311 {
 312         doc_probe (CONFIG_SYS_DOC_BASE);
 313 }
 314 #endif
 315
 316 #ifdef  CONFIG_PCI
 317 struct pci_controller hose;
 318
 319 extern void pci_mpc8250_init(struct pci_controller *);
 320
 321 void pci_init_board(void)
 322 {
 323         pci_mpc8250_init(&hose);
 324 }
 325 #endif
 326
 327 int board_eth_init(bd_t *bis)
 328 {
 329         return pci_eth_init(bis);
 330 }