board/davedenx/aria/aria.c

   1 /*
   2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3  * (C) Copyright 2009 Dave Srl www.dave.eu
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #include <common.h>
  26 #include <asm/bitops.h>
  27 #include <command.h>
  28 #include <asm/io.h>
  29 #include <asm/processor.h>
  30 #include <fdt_support.h>
  31 #ifdef CONFIG_MISC_INIT_R
  32 #include <i2c.h>
  33 #endif
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 extern int mpc5121_diu_init(void);
  38 extern void ide_set_reset(int idereset);
  39
  40 /* Clocks in use */
  41 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
  42                          CLOCK_SCCR1_LPC_EN |                           \
  43                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
  44                          CLOCK_SCCR1_PSCFIFO_EN |                       \
  45                          CLOCK_SCCR1_DDR_EN |                           \
  46                          CLOCK_SCCR1_FEC_EN |                           \
  47                          CLOCK_SCCR1_PATA_EN |                          \
  48                          CLOCK_SCCR1_PCI_EN |                           \
  49                          CLOCK_SCCR1_TPR_EN)
  50
  51 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
  52                          CLOCK_SCCR2_SPDIF_EN |         \
  53                          CLOCK_SCCR2_DIU_EN |           \
  54                          CLOCK_SCCR2_I2C_EN)
  55
  56 #define CSAW_START(start)       ((start) & 0xFFFF0000)
  57 #define CSAW_STOP(start, size)  (((start) + (size) - 1) >> 16)
  58
  59 long int fixed_sdram(void);
  60
  61 int board_early_init_f(void)
  62 {
  63         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  64         u32 spridr;
  65
  66         /*
  67          * Initialize Local Window for the On Board FPGA access
  68          */
  69         out_be32(&im->sysconf.lpcs2aw,
  70                 CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
  71                 CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
  72         );
  73         out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
  74
  75         /*
  76          * According to MPC5121e RM, configuring local access windows should
  77          * be followed by a dummy read of the config register that was
  78          * modified last and an isync
  79          */
  80         in_be32(&im->sysconf.lpcs2aw);
  81         __asm__ __volatile__ ("isync");
  82
  83         /*
  84          * Initialize Local Window for the On Board SRAM access
  85          */
  86         out_be32(&im->sysconf.lpcs6aw,
  87                 CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
  88                 CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
  89         );
  90         out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
  91
  92         /*
  93          * According to MPC5121e RM, configuring local access windows should
  94          * be followed by a dummy read of the config register that was
  95          * modified last and an isync
  96          */
  97         in_be32(&im->sysconf.lpcs6aw);
  98         __asm__ __volatile__ ("isync");
  99
 100         /*
 101          * Configure Flash Speed
 102          */
 103         out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
 104
 105         spridr = in_be32(&im->sysconf.spridr);
 106
 107         if (SVR_MJREV(spridr) >= 2)
 108                 out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
 109
 110         /*
 111          * Enable clocks
 112          */
 113         out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
 114         out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
 115 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
 116         setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
 117 #endif
 118
 119         return 0;
 120 }
 121
 122 phys_size_t initdram (int board_type)
 123 {
 124         return fixed_sdram();
 125 }
 126
 127 /*
 128  * fixed sdram init:
 129  * The board doesn't use memory modules that have serial presence
 130  * detect or similar mechanism for discovery of the DRAM settings
 131  */
 132 long int fixed_sdram (void)
 133 {
 134         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 135         u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 136         u32 msize_log2 = __ilog2(msize);
 137         u32 i;
 138
 139         /* Initialize IO Control */
 140         out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
 141
 142         /* Initialize DDR Local Window */
 143         out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
 144         out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
 145
 146         /*
 147          * According to MPC5121e RM, configuring local access windows should
 148          * be followed by a dummy read of the config register that was
 149          * modified last and an isync
 150          */
 151         in_be32(&im->sysconf.ddrlaw.ar);
 152         __asm__ __volatile__ ("isync");
 153
 154         /* Enable DDR */
 155         out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
 156
 157         /* Initialize DDR Priority Manager */
 158         out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
 159         out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
 160         out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
 161         out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
 162         out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
 163         out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
 164         out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
 165         out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
 166         out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
 167         out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
 168         out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
 169         out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
 170         out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
 171         out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
 172         out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
 173         out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
 174         out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
 175         out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
 176         out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
 177         out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
 178         out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
 179         out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
 180         out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
 181
 182         /* Initialize MDDRC */
 183         out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
 184         out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
 185         out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
 186         out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
 187
 188         /* Initialize DDR */
 189         for (i = 0; i < 10; i++)
 190                 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
 191
 192         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
 193         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
 194         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
 195         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
 196         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
 197         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
 198         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
 199         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
 200         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
 201         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
 202         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
 203         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
 204         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
 205         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
 206         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
 207         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
 208         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
 209         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
 210         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
 211         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
 212         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
 213
 214         /* Start MDDRC */
 215         out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
 216         out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
 217
 218         return msize;
 219 }
 220
 221 int misc_init_r(void)
 222 {
 223         u32 tmp;
 224
 225         /* we use I2C-2 for on-board eeprom */
 226         i2c_set_bus_num(2);
 227
 228         tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
 229         printf("FPGA:  %u-%u.%u.%u\n",
 230                 (tmp & 0xFF000000) >> 24,
 231                 (tmp & 0x00FF0000) >> 16,
 232                 (tmp & 0x0000FF00) >>  8,
 233                  tmp & 0x000000FF
 234         );
 235
 236 #ifdef CONFIG_FSL_DIU_FB
 237 # if    !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
 238         mpc5121_diu_init();
 239 # endif
 240 #endif
 241         return 0;
 242 }
 243
 244 static  iopin_t ioregs_init[] = {
 245         /*
 246          * FEC
 247          */
 248
 249         /* FEC on PSCx_x*/
 250         {
 251                 offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
 252                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 253                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 254         },
 255         {
 256                 offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
 257                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 258                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 259         },
 260         {
 261                 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
 262                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 263                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 264         },
 265
 266         /*
 267          * DIU
 268          */
 269         /* FUNC2=DIU CLK */
 270         {
 271                 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
 272                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 273                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 274         },
 275         /* FUNC2=DIU_HSYNC */
 276         {
 277                 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
 278                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 279                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 280         },
 281         /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
 282         {
 283                 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
 284                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 285                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 286         },
 287         /*
 288          * On board SRAM
 289          */
 290         /* FUNC2=/LPC CS6 */
 291         {
 292                 offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
 293                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 294                 IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
 295         },
 296 };
 297
 298
 299 int checkboard (void)
 300 {
 301         puts("Board: ARIA\n");
 302
 303         /* initialize function mux & slew rate IO inter alia on IO Pins  */
 304
 305         iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
 306
 307         return 0;
 308 }
 309
 310 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 311 void ft_board_setup(void *blob, bd_t *bd)
 312 {
 313         ft_cpu_setup(blob, bd);
 314         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 315 }
 316 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */