board/davedenx/qong/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
   3  *
   4  * Based on board/freescale/mx31ads/lowlevel_init.S
   5  * by Guennadi Liakhovetski.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <asm/arch/mx31-regs.h>
  24
  25 .macro REG reg, val
  26         ldr r2, =\reg
  27         ldr r3, =\val
  28         str r3, [r2]
  29 .endm
  30
  31 .macro REG8 reg, val
  32         ldr r2, =\reg
  33         ldr r3, =\val
  34         strb r3, [r2]
  35 .endm
  36
  37 .macro DELAY loops
  38         ldr r2, =\loops
  39 1:
  40         subs    r2, r2, #1
  41         nop
  42         bcs 1b
  43 .endm
  44
  45 /* RedBoot: To support 133MHz DDR */
  46 .macro init_drive_strength
  47         /*
  48          * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
  49          * in SW_PAD_CTL registers
  50          */
  51
  52         /* SDCLK */
  53         ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
  54         ldr r0, [r1, #0x6C]
  55         bic r0, r0, #(1 << 12)
  56         str r0, [r1, #0x6C]
  57
  58         /* CAS */
  59         ldr r0, [r1, #0x70]
  60         bic r0, r0, #(1 << 22)
  61         str r0, [r1, #0x70]
  62
  63         /* RAS */
  64         ldr r0, [r1, #0x74]
  65         bic r0, r0, #(1 << 2)
  66         str r0, [r1, #0x74]
  67
  68         /* CS2 (CSD0) */
  69         ldr r0, [r1, #0x7C]
  70         bic r0, r0, #(1 << 22)
  71         str r0, [r1, #0x7C]
  72
  73         /* DQM3 */
  74         ldr r0, [r1, #0x84]
  75         bic r0, r0, #(1 << 22)
  76         str r0, [r1, #0x84]
  77
  78         /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
  79         ldr r2, =22     /* (0x2E0 - 0x288) / 4 = 22 */
  80 pad_loop:
  81         ldr r0, [r1, #0x88]
  82         bic r0, r0, #(1 << 22)
  83         bic r0, r0, #(1 << 12)
  84         bic r0, r0, #(1 << 2)
  85         str r0, [r1, #0x88]
  86         add r1, r1, #4
  87         subs r2, r2, #0x1
  88         bne pad_loop
  89 .endm /* init_drive_strength */
  90
  91 .globl lowlevel_init
  92 lowlevel_init:
  93
  94         init_drive_strength
  95
  96         /* Image Processing Unit: */
  97         /* Too early to switch display on? */
  98         /* Switch on Display Interface */
  99         REG     IPU_CONF, IPU_CONF_DI_EN
 100         /* Clock Control Module: */
 101         REG     CCM_CCMR, 0x074B0BF5            /* Use CKIH, MCU PLL off */
 102
 103         DELAY 0x40000
 104
 105         REG     CCM_CCMR, 0x074B0BF5 | CCMR_MPE                 /* MCU PLL on */
 106         /* Switch to MCU PLL */
 107         REG     CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
 108
 109         /* 399-133-66.5 */
 110         ldr     r0, =CCM_BASE
 111         ldr     r1, =0xFF871650
 112         /* PDR0 */
 113         str     r1, [r0, #0x4]
 114         ldr     r1, MPCTL_PARAM_399
 115         /* MPCTL */
 116         str     r1, [r0, #0x10]
 117
 118         /* Set UPLL=240MHz, USB=60MHz */
 119         ldr     r1, =0x49FCFE7F
 120         /* PDR1 */
 121         str     r1, [r0, #0x8]
 122         ldr     r1, UPCTL_PARAM_240
 123         /* UPCTL */
 124         str     r1, [r0, #0x14]
 125         /* default CLKO to 1/8 of the ARM core */
 126         mov     r1, #0x00000208
 127         /* COSR */
 128         str     r1, [r0, #0x1c]
 129
 130         /* Default: 1, 4, 12, 1 */
 131         REG     CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
 132
 133         /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
 134         REG     0xB8001010, 0x00000004
 135         REG     0xB8001004, ((3 << 21) | /* tXP */      \
 136                              (0 << 20) | /* tWTR */     \
 137                              (2 << 18) | /* tRP */      \
 138                              (1 << 16) | /* tMRD */     \
 139                              (0 << 15) | /* tWR */      \
 140                              (5 << 12) | /* tRAS */     \
 141                              (1 << 10) | /* tRRD */     \
 142                              (3 << 8)  | /* tCAS */     \
 143                              (2 << 4)  | /* tRCD */     \
 144                              (7 << 0)    /* tRC */ )
 145         REG     0xB8001000, 0x92100000
 146         REG     0x80000f00, 0x12344321
 147         REG     0xB8001000, 0xa2100000
 148         REG     0x80000000, 0x12344321
 149         REG     0x80000000, 0x12344321
 150         REG     0xB8001000, 0xb2100000
 151         REG8    0x80000033, 0xda
 152         REG8    0x81000000, 0xff
 153         REG     0xB8001000, ((1 << 31) |                                \
 154                              (0 << 28) |                                \
 155                              (0 << 27) |                                \
 156                              (3 << 24) | /* 14 rows */                  \
 157                              (2 << 20) | /* 10 cols */                  \
 158                              (2 << 16) |                                \
 159                              (4 << 13) | /* 3.91us (64ms/16384) */      \
 160                              (0 << 10) |                                \
 161                              (0 << 8)  |                                \
 162                              (1 << 7)  |                                \
 163                              (0 << 0))
 164         REG     0x80000000, 0xDEADBEEF
 165         REG     0xB8001010, 0x0000000c
 166
 167         mov     pc, lr
 168
 169 MPCTL_PARAM_399:
 170         .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
 171 UPCTL_PARAM_240:
 172         .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3  << 0))