2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * Based on da850evm.c. Original Copyrights follow:
6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <spi_flash.h>
30 #include <asm/arch/hardware.h>
31 #include <asm/ti-common/davinci_nand.h>
33 #include <asm/errno.h>
34 #include <asm/arch/davinci_misc.h>
35 #ifdef CONFIG_DAVINCI_MMC
37 #include <asm/arch/sdmmc_defs.h>
40 DECLARE_GLOBAL_DATA_PTR
;
42 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
44 #ifdef CONFIG_DAVINCI_MMC
45 /* MMC0 pin muxer settings */
46 const struct pinmux_config mmc0_pins
[] = {
47 /* GP0[11] is required for SD to work on Rev 3 EVMs */
48 { pinmux(0), 8, 4 }, /* GP0[11] */
49 { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
50 { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
51 { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
52 { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
53 { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
54 { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
55 /* LCDK supports only 4-bit mode, remaining pins are not configured */
59 /* UART pin muxer settings */
60 static const struct pinmux_config uart_pins
[] = {
67 #ifdef CONFIG_DRIVER_TI_EMAC
68 static const struct pinmux_config emac_pins
[] = {
87 #endif /* CONFIG_DRIVER_TI_EMAC */
89 /* I2C pin muxer settings */
90 static const struct pinmux_config i2c_pins
[] = {
95 #ifdef CONFIG_NAND_DAVINCI
96 const struct pinmux_config nand_pins
[] = {
117 { pinmux(12), 1, 5 },
123 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
129 const struct pinmux_resource pinmuxes
[] = {
130 PINMUX_ITEM(uart_pins
),
131 PINMUX_ITEM(i2c_pins
),
132 #ifdef CONFIG_NAND_DAVINCI
133 PINMUX_ITEM(nand_pins
),
137 const int pinmuxes_size
= ARRAY_SIZE(pinmuxes
);
139 const struct lpsc_resource lpsc
[] = {
140 { DAVINCI_LPSC_AEMIF
}, /* NAND, NOR */
141 { DAVINCI_LPSC_SPI1
}, /* Serial Flash */
142 { DAVINCI_LPSC_EMAC
}, /* image download */
143 { DAVINCI_LPSC_UART2
}, /* console */
144 { DAVINCI_LPSC_GPIO
},
145 #ifdef CONFIG_DAVINCI_MMC
146 { DAVINCI_LPSC_MMC_SD
},
150 const int lpsc_size
= ARRAY_SIZE(lpsc
);
152 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
153 #define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
157 * get_board_rev() - setup to pass kernel board revision information
159 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
165 u32
get_board_rev(void)
170 int board_early_init_f(void)
173 * Power on required peripherals
174 * ARM does not have access by default to PSC0 and PSC1
175 * assuming here that the DSP bootloader has set the IOPU
176 * such that PSC access is available to ARM
178 if (da8xx_configure_lpsc_items(lpsc
, ARRAY_SIZE(lpsc
)))
186 #ifndef CONFIG_USE_IRQ
190 /* arch number of the board */
191 gd
->bd
->bi_arch_number
= MACH_TYPE_OMAPL138_LCDK
;
193 /* address of boot parameters */
194 gd
->bd
->bi_boot_params
= LINUX_BOOT_PARAM_ADDR
;
197 /* setup the SUSPSRC for ARM to control emulation suspend */
198 writel(readl(&davinci_syscfg_regs
->suspsrc
) &
199 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC
| DAVINCI_SYSCFG_SUSPSRC_I2C
|
200 DAVINCI_SYSCFG_SUSPSRC_SPI1
| DAVINCI_SYSCFG_SUSPSRC_TIMER0
|
201 DAVINCI_SYSCFG_SUSPSRC_UART2
),
202 &davinci_syscfg_regs
->suspsrc
);
204 /* configure pinmux settings */
205 if (davinci_configure_pin_mux_items(pinmuxes
, ARRAY_SIZE(pinmuxes
)))
208 #ifdef CONFIG_NAND_DAVINCI
210 * NAND CS setup - cycle counts based on da850evm NAND timings in the
211 * Linux kernel @ 25MHz EMIFA
213 writel((DAVINCI_ABCR_WSETUP(15) |
214 DAVINCI_ABCR_WSTROBE(63) |
215 DAVINCI_ABCR_WHOLD(7) |
216 DAVINCI_ABCR_RSETUP(15) |
217 DAVINCI_ABCR_RSTROBE(63) |
218 DAVINCI_ABCR_RHOLD(7) |
220 DAVINCI_ABCR_ASIZE_16BIT
),
221 &davinci_emif_regs
->ab2cr
); /* CS3 */
225 #ifdef CONFIG_DAVINCI_MMC
226 if (davinci_configure_pin_mux(mmc0_pins
, ARRAY_SIZE(mmc0_pins
)) != 0)
230 #ifdef CONFIG_DRIVER_TI_EMAC
231 if (davinci_configure_pin_mux(emac_pins
, ARRAY_SIZE(emac_pins
)) != 0)
233 davinci_emac_mii_mode_sel(HAS_RMII
);
234 #endif /* CONFIG_DRIVER_TI_EMAC */
236 /* enable the console UART */
237 writel((DAVINCI_UART_PWREMU_MGMT_FREE
| DAVINCI_UART_PWREMU_MGMT_URRST
|
238 DAVINCI_UART_PWREMU_MGMT_UTRST
),
239 &davinci_uart2_ctrl_regs
->pwremu_mgmt
);
244 #ifdef CONFIG_DRIVER_TI_EMAC
247 * Initializes on-board ethernet controllers.
249 int board_eth_init(bd_t
*bis
)
251 if (!davinci_emac_initialize()) {
252 printf("Error: Ethernet init failed!\n");
259 #endif /* CONFIG_DRIVER_TI_EMAC */
261 #define CFG_MAC_ADDR_SPI_BUS 0
262 #define CFG_MAC_ADDR_SPI_CS 0
263 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
264 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
266 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
268 static int get_mac_addr(u8
*addr
)
270 /* Need to find a way to get MAC ADDRESS */
274 void dsp_lpsc_on(unsigned domain
, unsigned int id
)
276 dv_reg_p mdstat
, mdctl
, ptstat
, ptcmd
;
277 struct davinci_psc_regs
*psc_regs
;
279 psc_regs
= davinci_psc0_regs
;
280 mdstat
= &psc_regs
->psc0
.mdstat
[id
];
281 mdctl
= &psc_regs
->psc0
.mdctl
[id
];
282 ptstat
= &psc_regs
->ptstat
;
283 ptcmd
= &psc_regs
->ptcmd
;
285 while (*ptstat
& (0x1 << domain
))
288 if ((*mdstat
& 0x1f) == 0x03)
289 return; /* Already on and enabled */
293 *ptcmd
= 0x1 << domain
;
295 while (*ptstat
& (0x1 << domain
))
297 while ((*mdstat
& 0x1f) != 0x03)
298 ; /* Probably an overkill... */
301 static void dspwake(void)
303 unsigned *resetvect
= (unsigned *)DAVINCI_L3CBARAM_BASE
;
305 /* if the device is ARM only, return */
306 if ((REG(CHIP_REV_ID_REG
) & 0x3f) == 0x10)
309 if (!strcmp(getenv("dspwake"), "no"))
312 *resetvect
++ = 0x1E000; /* DSP Idle */
313 /* clear out the next 10 words as NOP */
314 memset(resetvect
, 0, sizeof(unsigned) * 10);
316 /* setup the DSP reset vector */
317 REG(HOST1CFG
) = DAVINCI_L3CBARAM_BASE
;
319 dsp_lpsc_on(1, DAVINCI_LPSC_GEM
);
320 REG(PSC0_MDCTL
+ (15 * 4)) |= 0x100;
323 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
328 int rmii_hw_init(void)
332 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
334 int misc_init_r(void)
336 uint8_t tmp
[20], addr
[10];
339 if (getenv("ethaddr") == NULL
) {
340 /* Read Ethernet MAC address from EEPROM */
341 if (dvevm_read_mac_address(addr
)) {
342 /* Set Ethernet MAC address from EEPROM */
343 davinci_sync_env_enetaddr(addr
);
348 if (is_multicast_ethaddr(addr
) || is_zero_ethaddr(addr
)) {
349 printf("Invalid MAC address read.\n");
352 sprintf((char *)tmp
, "%02x:%02x:%02x:%02x:%02x:%02x", addr
[0],
353 addr
[1], addr
[2], addr
[3], addr
[4], addr
[5]);
355 setenv("ethaddr", (char *)tmp
);
357 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
358 /* Select RMII fucntion through the expander */
360 printf("RMII hardware init failed!!!\n");
368 #ifdef CONFIG_DAVINCI_MMC
369 static struct davinci_mmc mmc_sd0
= {
370 .reg_base
= (struct davinci_mmc_regs
*)DAVINCI_MMC_SD0_BASE
,
371 .host_caps
= MMC_MODE_4BIT
, /* DA850 supports only 4-bit SD/MMC */
372 .voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
,
373 .version
= MMC_CTLR_VERSION_2
,
376 int board_mmc_init(bd_t
*bis
)
378 mmc_sd0
.input_clk
= clk_get(DAVINCI_MMCSD_CLKID
);
380 /* Add slot-0 to mmc subsystem */
381 return davinci_mmc_init(bis
, &mmc_sd0
);