board/davinci/dv-evm/dv_board.c

   1 /*
   2  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   3  *
   4  * Parts are shamelessly stolen from various TI sources, original copyright
   5  * follows:
   6  * -----------------------------------------------------------------
   7  *
   8  * Copyright (C) 2004 Texas Instruments.
   9  *
  10  * ----------------------------------------------------------------------------
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  * ----------------------------------------------------------------------------
  25  */
  26
  27 #include <common.h>
  28 #include <i2c.h>
  29 #include <asm/arch/hardware.h>
  30 #include <asm/arch/emac_defs.h>
  31
  32 #define MACH_TYPE_DAVINCI_EVM           901
  33
  34 extern void     i2c_init(int speed, int slaveaddr);
  35 extern void     timer_init(void);
  36 extern int      eth_hw_init(void);
  37 extern phy_t    phy;
  38
  39
  40 /* Works on Always On power domain only (no PD argument) */
  41 void lpsc_on(unsigned int id)
  42 {
  43         dv_reg_p        mdstat, mdctl;
  44
  45         if (id >= DAVINCI_LPSC_GEM)
  46                 return;                 /* Don't work on DSP Power Domain */
  47
  48         mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
  49         mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
  50
  51         while (REG(PSC_PTSTAT) & 0x01) {;}
  52
  53         if ((*mdstat & 0x1f) == 0x03)
  54                 return;                 /* Already on and enabled */
  55
  56         *mdctl |= 0x03;
  57
  58         /* Special treatment for some modules as for sprue14 p.7.4.2 */
  59         if (    (id == DAVINCI_LPSC_VPSSSLV) ||
  60                 (id == DAVINCI_LPSC_EMAC) ||
  61                 (id == DAVINCI_LPSC_EMAC_WRAPPER) ||
  62                 (id == DAVINCI_LPSC_MDIO) ||
  63                 (id == DAVINCI_LPSC_USB) ||
  64                 (id == DAVINCI_LPSC_ATA) ||
  65                 (id == DAVINCI_LPSC_VLYNQ) ||
  66                 (id == DAVINCI_LPSC_UHPI) ||
  67                 (id == DAVINCI_LPSC_DDR_EMIF) ||
  68                 (id == DAVINCI_LPSC_AEMIF) ||
  69                 (id == DAVINCI_LPSC_MMC_SD) ||
  70                 (id == DAVINCI_LPSC_MEMSTICK) ||
  71                 (id == DAVINCI_LPSC_McBSP) ||
  72                 (id == DAVINCI_LPSC_GPIO)
  73            )
  74                 *mdctl |= 0x200;
  75
  76         REG(PSC_PTCMD) = 0x01;
  77
  78         while (REG(PSC_PTSTAT) & 0x03) {;}
  79         while ((*mdstat & 0x1f) != 0x03) {;}    /* Probably an overkill... */
  80 }
  81
  82 void dsp_on(void)
  83 {
  84         int     i;
  85
  86         if (REG(PSC_PDSTAT1) & 0x1f)
  87                 return;                 /* Already on */
  88
  89         REG(PSC_GBLCTL) |= 0x01;
  90         REG(PSC_PDCTL1) |= 0x01;
  91         REG(PSC_PDCTL1) &= ~0x100;
  92         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
  93         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
  94         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
  95         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
  96         REG(PSC_PTCMD) = 0x02;
  97
  98         for (i = 0; i < 100; i++) {
  99                 if (REG(PSC_EPCPR) & 0x02)
 100                         break;
 101         }
 102
 103         REG(PSC_CHP_SHRTSW) = 0x01;
 104         REG(PSC_PDCTL1) |= 0x100;
 105         REG(PSC_EPCCR) = 0x02;
 106
 107         for (i = 0; i < 100; i++) {
 108                 if (!(REG(PSC_PTSTAT) & 0x02))
 109                         break;
 110         }
 111
 112         REG(PSC_GBLCTL) &= ~0x1f;
 113 }
 114
 115
 116 int board_init(void)
 117 {
 118         DECLARE_GLOBAL_DATA_PTR;
 119
 120         /* arch number of the board */
 121         gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
 122
 123         /* address of boot parameters */
 124         gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
 125
 126         /* Workaround for TMS320DM6446 errata 1.3.22 */
 127         REG(PSC_SILVER_BULLET) = 0;
 128
 129         /* Power on required peripherals */
 130         lpsc_on(DAVINCI_LPSC_EMAC);
 131         lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
 132         lpsc_on(DAVINCI_LPSC_MDIO);
 133         lpsc_on(DAVINCI_LPSC_I2C);
 134         lpsc_on(DAVINCI_LPSC_UART0);
 135         lpsc_on(DAVINCI_LPSC_TIMER1);
 136         lpsc_on(DAVINCI_LPSC_GPIO);
 137
 138         /* Powerup the DSP */
 139         dsp_on();
 140
 141         /* Bringup UART0 out of reset */
 142         REG(UART0_PWREMU_MGMT) = 0x0000e003;
 143
 144         /* Enable GIO3.3V cells used for EMAC */
 145         REG(VDD3P3V_PWDN) = 0;
 146
 147         /* Enable UART0 MUX lines */
 148         REG(PINMUX1) |= 1;
 149
 150         /* Enable EMAC and AEMIF pins */
 151         REG(PINMUX0) = 0x80000c1f;
 152
 153         /* Enable I2C pin Mux */
 154         REG(PINMUX1) |= (1 << 7);
 155
 156         /* Set the Bus Priority Register to appropriate value */
 157         REG(VBPR) = 0x20;
 158
 159         timer_init();
 160
 161         return(0);
 162 }
 163
 164 int misc_init_r (void)
 165 {
 166         u_int8_t        tmp[20], buf[10];
 167         int             i = 0;
 168         int             clk = 0;
 169
 170         clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
 171
 172         printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
 173         printf ("DDR Clock : %dMHz\n", (clk / 2));
 174
 175         /* Set Ethernet MAC address from EEPROM */
 176         if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) {
 177                 printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR);
 178         } else {
 179                 tmp[0] = 0xff;
 180                 for (i = 0; i < 6; i++)
 181                         tmp[0] &= buf[i];
 182
 183                 if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
 184                         sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
 185                                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
 186                         setenv("ethaddr", (char *)&tmp[0]);
 187                 }
 188         }
 189
 190         if (!eth_hw_init()) {
 191                 printf("ethernet init failed!\n");
 192         } else {
 193                 printf("ETH PHY   : %s\n", phy.name);
 194         }
 195
 196         i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1);
 197
 198         setenv ("videostd", ((i  & 0x80) ? "pal" : "ntsc"));
 199
 200         return(0);
 201 }
 202
 203 int dram_init(void)
 204 {
 205         DECLARE_GLOBAL_DATA_PTR;
 206
 207         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 208         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 209
 210         return(0);
 211 }