board/davinci/sffsdr/sffsdr.c

   1 /*
   2  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   3  *
   4  * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
   5  * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
   6  *
   7  * Parts are shamelessly stolen from various TI sources, original copyright
   8  * follows:
   9  *
  10  * Copyright (C) 2004 Texas Instruments.
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29
  30 #include <common.h>
  31 #include <i2c.h>
  32 #include <asm/arch/hardware.h>
  33 #include <asm/arch/emac_defs.h>
  34 #include "../common/psc.h"
  35 #include "../common/misc.h"
  36
  37 #define DAVINCI_A3CR     (0x01E00014)   /* EMIF-A CS3 config register. */
  38 #define DAVINCI_A3CR_VAL (0x3FFFFFFD)   /* EMIF-A CS3 value for FPGA. */
  39
  40 #define INTEGRITY_SYSCFG_OFFSET    0x7E8
  41 #define INTEGRITY_CHECKWORD_OFFSET 0x7F8
  42 #define INTEGRITY_CHECKWORD_VALUE  0x10ADBEEF
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 int board_init(void)
  47 {
  48         /* arch number of the board */
  49         gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
  50
  51         /* address of boot parameters */
  52         gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  53
  54         /* Workaround for TMS320DM6446 errata 1.3.22 */
  55         REG(PSC_SILVER_BULLET) = 0;
  56
  57         /* Power on required peripherals */
  58         lpsc_on(DAVINCI_LPSC_EMAC);
  59         lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
  60         lpsc_on(DAVINCI_LPSC_MDIO);
  61         lpsc_on(DAVINCI_LPSC_I2C);
  62         lpsc_on(DAVINCI_LPSC_UART0);
  63         lpsc_on(DAVINCI_LPSC_TIMER1);
  64         lpsc_on(DAVINCI_LPSC_GPIO);
  65
  66 #if !defined(CONFIG_SYS_USE_DSPLINK)
  67         /* Powerup the DSP */
  68         dsp_on();
  69 #endif /* CONFIG_SYS_USE_DSPLINK */
  70
  71         /* Bringup UART0 out of reset */
  72         REG(UART0_PWREMU_MGMT) = 0x0000e003;
  73
  74         /* Enable GIO3.3V cells used for EMAC */
  75         REG(VDD3P3V_PWDN) = 0;
  76
  77         /* Enable UART0 MUX lines */
  78         REG(PINMUX1) |= 1;
  79
  80         /* Enable EMAC and AEMIF pins */
  81         REG(PINMUX0) = 0x80000c1f;
  82
  83         /* Enable I2C pin Mux */
  84         REG(PINMUX1) |= (1 << 7);
  85
  86         /* Set the Bus Priority Register to appropriate value */
  87         REG(VBPR) = 0x20;
  88
  89         timer_init();
  90
  91         return(0);
  92 }
  93
  94 /* Read ethernet MAC address from Integrity data structure inside EEPROM.
  95  * Returns 1 if found, 0 otherwise.
  96  */
  97 static int sffsdr_read_mac_address(uint8_t *buf)
  98 {
  99         u_int32_t value, mac[2], address;
 100
 101         /* Read Integrity data structure checkword. */
 102         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
 103                      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
 104                 goto err;
 105         if (value != INTEGRITY_CHECKWORD_VALUE)
 106                 return 0;
 107
 108         /* Read SYSCFG structure offset. */
 109         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
 110                      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
 111                 goto err;
 112         address = 0x800 + (int) value; /* Address of SYSCFG structure. */
 113
 114         /* Read NET CONFIG structure offset. */
 115         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
 116                      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
 117                 goto err;
 118         address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
 119         address += 12; /* Address of NET INTERFACE CONFIG structure. */
 120
 121         /* Read NET INTERFACE CONFIG 2 structure offset. */
 122         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
 123                      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
 124                 goto err;
 125         address = 0x800 + 16 + (int) value;     /* Address of NET INTERFACE
 126                                                  * CONFIG 2 structure. */
 127
 128         /* Read MAC address. */
 129         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
 130                      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
 131                 goto err;
 132
 133         buf[0] = mac[0] >> 24;
 134         buf[1] = mac[0] >> 16;
 135         buf[2] = mac[0] >> 8;
 136         buf[3] = mac[0];
 137         buf[4] = mac[1] >> 24;
 138         buf[5] = mac[1] >> 16;
 139
 140         return 1; /* Found */
 141
 142 err:
 143         printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
 144         return 0;
 145 }
 146
 147 /* Platform dependent initialisation. */
 148 int misc_init_r(void)
 149 {
 150         uint8_t i2cbuf;
 151         uint8_t eeprom_enetaddr[6];
 152
 153         /* EMIF-A CS3 configuration for FPGA. */
 154         REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
 155
 156         dv_display_clk_infos();
 157
 158         /* Configure I2C switch (PCA9543) to enable channel 0. */
 159         i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
 160         if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
 161                       CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
 162                 printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR);
 163                 return 1;
 164         }
 165
 166         /* Read Ethernet MAC address from EEPROM if available. */
 167         if (sffsdr_read_mac_address(eeprom_enetaddr))
 168                 dv_configure_mac_address(eeprom_enetaddr);
 169
 170         if (!eth_hw_init())
 171                 printf("Ethernet init failed\n");
 172
 173         return(0);
 174 }