board/delta/lowlevel_init.S

   1 /*
   2  * Most of this taken from Redboot hal_platform_setup.h with cleanup
   3  *
   4  * NOTE: I haven't clean this up considerably, just enough to get it
   5  * running. See hal_platform_setup.h for the source. See
   6  * board/cradle/lowlevel_init.S for another PXA250 setup that is
   7  * much cleaner.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <version.h>
  30 #include <asm/arch/pxa-regs.h>
  31
  32 DRAM_SIZE:  .long   CFG_DRAM_SIZE
  33
  34 /* wait for coprocessor write complete */
  35    .macro CPWAIT reg
  36    mrc  p15,0,\reg,c2,c0,0
  37    mov  \reg,\reg
  38    sub  pc,pc,#4
  39    .endm
  40
  41
  42 .macro wait time
  43         ldr             r2, =OSCR
  44         mov             r3, #0
  45         str             r3, [r2]
  46 0:
  47         ldr             r3, [r2]
  48         cmp             r3, \time
  49         bls             0b
  50 .endm
  51
  52 /*
  53  *      Memory setup
  54  */
  55
  56 .globl lowlevel_init
  57 lowlevel_init:
  58         /* Set up GPIO pins first ----------------------------------------- */
  59         mov      r10, lr
  60
  61         /*  Configure GPIO  Pins 97, 98 UART1 / altern. Fkt. 1 */
  62         ldr             r0, =GPIO97
  63         ldr             r1, =0x801
  64         str             r1, [r0]
  65
  66         ldr             r0, =GPIO98
  67         ldr             r1, =0x801
  68         str             r1, [r0]
  69
  70         /* tebrandt - ASCR, clear the RDH bit */
  71         ldr             r0, =ASCR
  72         ldr             r1, [r0]
  73         bic             r1, r1, #0x80000000
  74         str             r1, [r0]
  75
  76         /* ---------------------------------------------------------------- */
  77         /* Enable memory interface                                          */
  78         /* ---------------------------------------------------------------- */
  79
  80         /* ---------------------------------------------------------------- */
  81         /* Step 1: Wait for at least 200 microsedonds to allow internal     */
  82         /*         clocks to settle. Only necessary after hard reset...     */
  83         /*         FIXME: can be optimized later                            */
  84         /* ---------------------------------------------------------------- */
  85 ;       wait #300
  86
  87 mem_init:
  88
  89 #define NEW_SDRAM_INIT 1
  90 #ifdef NEW_SDRAM_INIT
  91
  92         /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
  93         ldr             r0, =ACCR
  94         ldr             r1, [r0]
  95         orr             r1, r1, #0x3000
  96         str             r1, [r0]
  97         ldr             r1, [r0]
  98
  99         /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
 100         ldr             r0, =MDCNFG
 101         ldr             r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
 102         /*      ldr             r1, =0x80000403 */
 103         str             r1, [r0]
 104         ldr             r1, [r0]        /* delay until written */
 105
 106         /* 3. wait nop power up waiting period (200ms)
 107          * optimization: Steps 4+6 can be done during this
 108          */
 109         wait #300
 110
 111         /* 4. Perform an initial Rcomp-calibration cycle */
 112         ldr             r0, =RCOMP
 113         ldr             r1, =0x80000000
 114         str             r1, [r0]
 115         ldr             r1, [r0]        /* delay until written */
 116         /* missing: program for automatic rcomp evaluation cycles */
 117
 118         /* 5. DDR DRAM strobe delay calibration */
 119         ldr             r0, =DDR_HCAL
 120         ldr             r1, =0x88000007
 121         str             r1, [r0]
 122         wait            #5
 123         ldr             r1, [r0]        /* delay until written */
 124
 125         /* Set MDMRS */
 126         ldr             r0, =MDMRS
 127         ldr             r1, =0x60000033
 128         str             r1, [r0]
 129         wait    #300
 130
 131         /* Configure MDREFR */
 132         ldr             r0, =MDREFR
 133         ldr             r1, =0x00000006
 134         str             r1, [r0]
 135         ldr             r1, [r0]
 136
 137         /* Enable the dynamic memory controller */
 138         ldr             r0, =MDCNFG
 139         ldr             r1, [r0]
 140         orr             r1, r1, #MDCNFG_DMCEN
 141         str             r1, [r0]
 142
 143
 144 #else /* NEW_SDRAM_INIT */
 145
 146         /* configure the MEMCLKCFG register */
 147         ldr             r1, =MEMCLKCFG
 148         ldr             r2, =0x00010001
 149         str             r2, [r1]             @ WRITE
 150         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 151
 152         /* set CSADRCFG[0] to data flash SRAM mode */
 153         ldr             r1, =CSADRCFG0
 154         ldr             r2, =0x00320809
 155         str             r2, [r1]             @ WRITE
 156         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 157
 158         /* set CSADRCFG[1] to data flash SRAM mode */
 159         ldr             r1, =CSADRCFG1
 160         ldr             r2, =0x00320809
 161         str             r2, [r1]             @ WRITE
 162         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 163
 164         /* set MSC 0 register for SRAM memory */
 165         ldr             r1, =MSC0
 166         ldr             r2, =0x11191119
 167         str             r2, [r1]             @ WRITE
 168         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 169
 170         /* set CSADRCFG[2] to data flash SRAM mode */
 171         ldr             r1, =CSADRCFG2
 172         ldr             r2, =0x00320809
 173         str             r2, [r1]             @ WRITE
 174         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 175
 176         /* set CSADRCFG[3] to VLIO mode */
 177         ldr             r1, =CSADRCFG3
 178         ldr             r2, =0x0032080B
 179         str             r2, [r1]             @ WRITE
 180         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 181
 182         /* set MSC 1 register for VLIO memory */
 183         ldr             r1, =MSC1
 184         ldr             r2, =0x123C1119
 185         str             r2, [r1]             @ WRITE
 186         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 187
 188 #if 0
 189         /* This does not work in Zylonite. -SC */
 190         ldr             r0, =0x15fffff0
 191         ldr             r1, =0xb10b
 192         str             r1, [r0]
 193         str             r1, [r0, #4]
 194 #endif
 195
 196         /* Configure ACCR Register */
 197         ldr             r0, =ACCR               @ ACCR
 198         ldr             r1, =0x0180b108
 199         str             r1, [r0]
 200         ldr             r1, [r0]
 201
 202         /* Configure MDCNFG Register */
 203         ldr             r0, =MDCNFG             @ MDCNFG
 204         ldr             r1, =0x403
 205         str             r1, [r0]
 206         ldr             r1, [r0]
 207
 208         /* Perform Resistive Compensation by configuring RCOMP register */
 209         ldr             r1, =RCOMP              @ RCOMP
 210         ldr             r2, =0x000000ff
 211         str             r2, [r1]
 212         ldr             r2, [r1]
 213
 214         /* Configure MDMRS Register for SDCS0 */
 215         ldr             r1, =MDMRS              @ MDMRS
 216         ldr             r2, =0x60000023
 217         ldr             r3, [r1]
 218         orr             r2, r2, r3
 219         str             r2, [r1]
 220         ldr             r2, [r1]
 221
 222         /* Configure MDMRS Register for SDCS1 */
 223         ldr             r1, =MDMRS              @ MDMRS
 224         ldr             r2, =0xa0000023
 225         ldr             r3, [r1]
 226         orr             r2, r2, r3
 227         str             r2, [r1]
 228         ldr             r2, [r1]
 229
 230         /* Configure MDREFR */
 231         ldr             r1, =MDREFR             @ MDREFR
 232         ldr             r2, =0x00000006
 233         str             r2, [r1]
 234         ldr             r2, [r1]
 235
 236         /* Configure EMPI */
 237         ldr             r1, =EMPI               @ EMPI
 238         ldr             r2, =0x80000000
 239         str             r2, [r1]
 240         ldr             r2, [r1]
 241
 242         /* Hardware DDR Read-Strobe Delay Calibration */
 243         ldr             r0, =DDR_HCAL           @ DDR_HCAL
 244         ldr             r1, =0x803ffc07     @ the offset is correct? -SC
 245         str             r1, [r0]
 246         wait            #5
 247         ldr             r1, [r0]
 248
 249         /* Here we assume the hardware calibration alwasy be successful. -SC */
 250         /* Set DMCEN bit in MDCNFG Register */
 251         ldr             r0, =MDCNFG             @ MDCNFG
 252         ldr             r1, [r0]
 253         orr             r1, r1, #0x40000000     @ enable SDRAM for Normal Access
 254         str             r1, [r0]
 255
 256 #endif /* NEW_SDRAM_INIT */
 257
 258 #ifndef CFG_SKIP_DRAM_SCRUB
 259         /* scrub/init SDRAM if enabled/present */
 260         ldr     r8, =CFG_DRAM_BASE      /* base address of SDRAM (CFG_DRAM_BASE) */
 261         ldr     r9, =CFG_DRAM_SIZE      /* size of memory to scrub (CFG_DRAM_SIZE) */
 262         mov     r0, #0                  /* scrub with 0x0000:0000 */
 263         mov     r1, #0
 264         mov     r2, #0
 265         mov     r3, #0
 266         mov     r4, #0
 267         mov     r5, #0
 268         mov     r6, #0
 269         mov     r7, #0
 270 10:     /* fastScrubLoop */
 271         subs    r9, r9, #32     /* 8 words/line */
 272         stmia   r8!, {r0-r7}
 273         beq     15f
 274         b       10b
 275 #endif /* CFG_SKIP_DRAM_SCRUB */
 276
 277 15:
 278         /* Mask all interrupts */
 279         mov     r1, #0
 280         mcr     p6, 0, r1, c1, c0, 0    @ ICMR
 281
 282         /* Disable software and data breakpoints */
 283         mov     r0, #0
 284         mcr     p15,0,r0,c14,c8,0  // ibcr0
 285         mcr     p15,0,r0,c14,c9,0  // ibcr1
 286         mcr     p15,0,r0,c14,c4,0  // dbcon
 287
 288         /* Enable all debug functionality */
 289         mov     r0,#0x80000000
 290         mcr     p14,0,r0,c10,c0,0  // dcsr
 291
 292 endlowlevel_init:
 293
 294         mov     pc, lr
 295
 296
 297 /*
 298 @********************************************************************************
 299 @ DDR calibration
 300 @
 301 @  This function is used to calibrate DQS delay lines.
 302 @ Monahans supports three ways to do it. One is software
 303 @ calibration. Two is hardware calibration. Three is hybrid
 304 @ calibration.
 305 @
 306 @ TBD
 307 @ -SC
 308 ddr_calibration:
 309
 310         @ Case 1:       Write the correct delay value once
 311         @ Configure DDR_SCAL Register
 312         ldr             r0, =DDR_SCAL           @ DDR_SCAL
 313 q       ldr             r1, =0xaf2f2f2f
 314         str             r1, [r0]
 315         ldr             r1, [r0]
 316 */
 317 /*      @ Case 2:       Software Calibration
 318         @ Write test pattern to memory
 319         ldr             r5, =0x0faf0faf         @ Data Pattern
 320         ldr             r4, =0xa0000000         @ DDR ram
 321         str             r5, [r4]
 322
 323         mov             r1, =0x0                @ delay count
 324         mov             r6, =0x0
 325         mov             r7, =0x0
 326 ddr_loop1:
 327         add             r1, r1, =0x1
 328         cmp             r1, =0xf
 329         ble             end_loop
 330         mov             r3, r1
 331         mov             r0, r1, lsl #30
 332         orr             r3, r3, r0
 333         mov             r0, r1, lsl #22
 334         orr             r3, r3, r0
 335         mov             r0, r1, lsl #14
 336         orr             r3, r3, r0
 337         orr             r3, r3, =0x80000000
 338         ldr             r2, =DDR_SCAL
 339         str             r3, [r2]
 340
 341         ldr             r2, [r4]
 342         cmp             r2, r5
 343         bne             ddr_loop1
 344         mov             r6, r1
 345 ddr_loop2:
 346         add             r1, r1, =0x1
 347         cmp             r1, =0xf
 348         ble             end_loop
 349         mov             r3, r1
 350         mov             r0, r1, lsl #30
 351         orr             r3, r3, r0
 352         mov             r0, r1, lsl #22
 353         orr             r3, r3, r0
 354         mov             r0, r1, lsl #14
 355         orr             r3, r3, r0
 356         orr             r3, r3, =0x80000000
 357         ldr             r2, =DDR_SCAL
 358         str             r3, [r2]
 359
 360         ldr             r2, [r4]
 361         cmp             r2, r5
 362         be              ddr_loop2
 363         mov             r7, r2
 364
 365         add             r3, r6, r7
 366         lsr             r3, r3, =0x1
 367         mov             r0, r1, lsl #30
 368         orr             r3, r3, r0
 369         mov             r0, r1, lsl #22
 370         orr             r3, r3, r0
 371         mov             r0, r1, lsl #14
 372         orr             r3, r3, r0
 373         orr             r3, r3, =0x80000000
 374         ldr             r2, =DDR_SCAL
 375
 376 end_loop:
 377
 378         @ Case 3:       Hardware Calibratoin
 379         ldr             r0, =DDR_HCAL           @ DDR_HCAL
 380         ldr             r1, =0x803ffc07     @ the offset is correct? -SC
 381         str             r1, [r0]
 382         wait            #5
 383         ldr             r1, [r0]
 384         mov             pc, lr
 385 */