board/digsy_mtc/digsy_mtc.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2005-2009
   9  * Modified for InterControl digsyMTC MPC5200 board by
  10  * Frank Bodammer, GCD Hard- & Software GmbH,
  11  *                 frank.bodammer@gcd-solutions.de
  12  *
  13  * (C) Copyright 2009
  14  * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #include <common.h>
  36 #include <mpc5xxx.h>
  37 #include <net.h>
  38 #include <pci.h>
  39 #include <asm/processor.h>
  40 #include <asm/io.h>
  41 #include "eeprom.h"
  42 #if defined(CONFIG_DIGSY_REV5)
  43 #include "is45s16800a2.h"
  44 #include <mtd/cfi_flash.h>
  45 #include <flash.h>
  46 #else
  47 #include "is42s16800a-7t.h"
  48 #endif
  49 #include <libfdt.h>
  50 #include <fdt_support.h>
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 extern int usb_cpu_init(void);
  55
  56 #if defined(CONFIG_DIGSY_REV5)
  57 /*
  58  * The M29W128GH needs a specail reset command function,
  59  * details see the doc/README.cfi file
  60  */
  61 void flash_cmd_reset(flash_info_t *info)
  62 {
  63         flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
  64 }
  65 #endif
  66
  67 #ifndef CONFIG_SYS_RAMBOOT
  68 static void sdram_start(int hi_addr)
  69 {
  70         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  71         long control = SDRAM_CONTROL | hi_addr_bit;
  72
  73         /* unlock mode register */
  74         out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
  75
  76         /* precharge all banks */
  77         out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
  78
  79         /* auto refresh */
  80         out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
  81
  82         /* set mode register */
  83         out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  84
  85         /* normal operation */
  86         out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
  87 }
  88 #endif
  89
  90 /*
  91  * ATTENTION: Although partially referenced initdram does NOT make real use
  92  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  93  *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  94  */
  95
  96 phys_size_t initdram(int board_type)
  97 {
  98         ulong dramsize = 0;
  99         ulong dramsize2 = 0;
 100         uint svr, pvr;
 101 #ifndef CONFIG_SYS_RAMBOOT
 102         ulong test1, test2;
 103
 104         /* setup SDRAM chip selects */
 105         out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
 106         out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
 107
 108         /* setup config registers */
 109         out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
 110         out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
 111
 112         /* find RAM size using SDRAM CS0 only */
 113         sdram_start(0);
 114         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
 115         sdram_start(1);
 116         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
 117         if (test1 > test2) {
 118                 sdram_start(0);
 119                 dramsize = test1;
 120         } else {
 121                 dramsize = test2;
 122         }
 123
 124         /* memory smaller than 1MB is impossible */
 125         if (dramsize < (1 << 20))
 126                 dramsize = 0;
 127
 128         /* set SDRAM CS0 size according to the amount of RAM found */
 129         if (dramsize > 0) {
 130                 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
 131                         (0x13 + __builtin_ffs(dramsize >> 20) - 1));
 132         } else {
 133                 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
 134         }
 135
 136         /* let SDRAM CS1 start right after CS0 */
 137         out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
 138
 139         /* find RAM size using SDRAM CS1 only */
 140         test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
 141                         0x08000000);
 142                 dramsize2 = test1;
 143
 144         /* memory smaller than 1MB is impossible */
 145         if (dramsize2 < (1 << 20))
 146                 dramsize2 = 0;
 147
 148         /* set SDRAM CS1 size according to the amount of RAM found */
 149         if (dramsize2 > 0) {
 150                 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
 151                         (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
 152         } else {
 153                 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
 154         }
 155
 156 #else /* CONFIG_SYS_RAMBOOT */
 157
 158         /* retrieve size of memory connected to SDRAM CS0 */
 159         dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
 160         if (dramsize >= 0x13)
 161                 dramsize = (1 << (dramsize - 0x13)) << 20;
 162         else
 163                 dramsize = 0;
 164
 165         /* retrieve size of memory connected to SDRAM CS1 */
 166         dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
 167         if (dramsize2 >= 0x13)
 168                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 169         else
 170                 dramsize2 = 0;
 171
 172 #endif /* CONFIG_SYS_RAMBOOT */
 173
 174         /*
 175          * On MPC5200B we need to set the special configuration delay in the
 176          * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 177          * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 178          *
 179          * "The SDelay should be written to a value of 0x00000004. It is
 180          * required to account for changes caused by normal wafer processing
 181          * parameters."
 182          */
 183         svr = get_svr();
 184         pvr = get_pvr();
 185         if ((SVR_MJREV(svr) >= 2) &&
 186             (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
 187                 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
 188
 189         return dramsize + dramsize2;
 190 }
 191
 192 int checkboard(void)
 193 {
 194         char *s = getenv("serial#");
 195
 196         puts ("Board: InterControl digsyMTC");
 197 #if defined(CONFIG_DIGSY_REV5)
 198         puts (" rev5");
 199 #endif
 200         if (s != NULL) {
 201                 puts(", ");
 202                 puts(s);
 203         }
 204         putc('\n');
 205
 206         return 0;
 207 }
 208
 209 int board_early_init_r(void)
 210 {
 211 #ifdef CONFIG_MPC52XX_SPI
 212         struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
 213 #endif
 214         /*
 215          * Now, when we are in RAM, enable flash write access for detection
 216          * process.  Note that CS_BOOT cannot be cleared when executing in
 217          * flash.
 218          */
 219         /* disable CS_BOOT */
 220         clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
 221         /* enable CS1 */
 222         setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
 223         /* enable CS0 */
 224         setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
 225
 226 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 227         /* Low level USB init, required for proper kernel operation */
 228         usb_cpu_init();
 229 #endif
 230 #ifdef CONFIG_MPC52XX_SPI
 231         /* GPT 6 Output Enable */
 232         out_be32(&gpt[6].emsr, 0x00000034);
 233         /* GPT 7 Output Enable */
 234         out_be32(&gpt[7].emsr, 0x00000034);
 235 #endif
 236
 237         return (0);
 238 }
 239
 240 void board_get_enetaddr (uchar * enet)
 241 {
 242         ushort read = 0;
 243         ushort addr_of_eth_addr = 0;
 244         ushort len_sys = 0;
 245         ushort len_sys_cfg = 0;
 246
 247         /* check identification word */
 248         eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
 249         if (read != EEPROM_IDENT)
 250                 return;
 251
 252         /* calculate offset of config area */
 253         eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
 254         eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
 255                 (uchar *)&len_sys_cfg, 2);
 256         addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
 257         if (addr_of_eth_addr >= EEPROM_LEN)
 258                 return;
 259
 260         eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
 261 }
 262
 263 int misc_init_r(void)
 264 {
 265         uchar enetaddr[6];
 266
 267         if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 268                 board_get_enetaddr(enetaddr);
 269                 eth_setenv_enetaddr("ethaddr", enetaddr);
 270         }
 271
 272         return 0;
 273 }
 274
 275 #ifdef CONFIG_PCI
 276 static struct pci_controller hose;
 277
 278 extern void pci_mpc5xxx_init(struct pci_controller *);
 279
 280 void pci_init_board(void)
 281 {
 282         pci_mpc5xxx_init(&hose);
 283 }
 284 #endif
 285
 286 #ifdef CONFIG_CMD_IDE
 287
 288 #ifdef CONFIG_IDE_RESET
 289
 290 void init_ide_reset(void)
 291 {
 292         debug ("init_ide_reset\n");
 293
 294         /* set gpio output value to 1 */
 295         setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 296         /* open drain output */
 297         setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 298         /* direction output */
 299         setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 300         /* enable gpio */
 301         setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 302
 303 }
 304
 305 void ide_set_reset(int idereset)
 306 {
 307         debug ("ide_reset(%d)\n", idereset);
 308
 309         /* set gpio output value to 0 */
 310         clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 311         /* open drain output */
 312         setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 313         /* direction output */
 314         setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 315         /* enable gpio */
 316         setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 317
 318         udelay(10000);
 319
 320         /* set gpio output value to 1 */
 321         setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 322         /* open drain output */
 323         setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 324         /* direction output */
 325         setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 326         /* enable gpio */
 327         setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 328 }
 329 #endif /* CONFIG_IDE_RESET */
 330 #endif /* CONFIG_CMD_IDE */
 331
 332 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 333 static void ft_delete_node(void *fdt, const char *compat)
 334 {
 335         int off = -1;
 336         int ret;
 337
 338         off = fdt_node_offset_by_compatible(fdt, -1, compat);
 339         if (off < 0) {
 340                 printf("Could not find %s node.\n", compat);
 341                 return;
 342         }
 343
 344         ret = fdt_del_node(fdt, off);
 345         if (ret < 0)
 346                 printf("Could not delete %s node.\n", compat);
 347 }
 348 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
 349 static void ft_adapt_flash_base(void *blob)
 350 {
 351         flash_info_t    *dev = &flash_info[0];
 352         int off;
 353         struct fdt_property *prop;
 354         int len;
 355         u32 *reg, *reg2;
 356
 357         off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
 358         if (off < 0) {
 359                 printf("Could not find fsl,mpc5200b-lpb node.\n");
 360                 return;
 361         }
 362
 363         /* found compatible property */
 364         prop = fdt_get_property_w(blob, off, "ranges", &len);
 365         if (prop) {
 366                 reg = reg2 = (u32 *)&prop->data[0];
 367
 368                 reg[2] = dev->start[0];
 369                 reg[3] = dev->size;
 370                 fdt_setprop(blob, off, "ranges", reg2, len);
 371         } else
 372                 printf("Could not find ranges\n");
 373 }
 374
 375 extern ulong flash_get_size (phys_addr_t base, int banknum);
 376
 377 /* Update the Flash Baseaddr settings */
 378 int update_flash_size (int flash_size)
 379 {
 380         volatile struct mpc5xxx_mmap_ctl *mm =
 381                 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
 382         flash_info_t    *dev;
 383         int     i;
 384         int size = 0;
 385         unsigned long base = 0x0;
 386         u32 *cs_reg = (u32 *)&mm->cs0_start;
 387
 388         for (i = 0; i < 2; i++) {
 389                 dev = &flash_info[i];
 390
 391                 if (dev->size) {
 392                         /* calculate new base addr for this chipselect */
 393                         base -= dev->size;
 394                         out_be32(cs_reg, START_REG(base));
 395                         cs_reg++;
 396                         out_be32(cs_reg, STOP_REG(base, dev->size));
 397                         cs_reg++;
 398                         /* recalculate the sectoraddr in the cfi driver */
 399                         size += flash_get_size(base, i);
 400                 }
 401         }
 402         flash_protect_default();
 403         gd->bd->bi_flashstart = base;
 404         return 0;
 405 }
 406 #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
 407
 408 void ft_board_setup(void *blob, bd_t *bd)
 409 {
 410         int phy_addr = CONFIG_PHY_ADDR;
 411         char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
 412
 413         ft_cpu_setup(blob, bd);
 414         /*
 415          * There are 2 RTC nodes in the DTS, so remove
 416          * the unneeded node here.
 417          */
 418 #if defined(CONFIG_DIGSY_REV5)
 419         ft_delete_node(blob, "dallas,ds1339");
 420 #else
 421         ft_delete_node(blob, "mc,rv3029c2");
 422 #endif
 423 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
 424 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 425         /* Update reg property in all nor flash nodes too */
 426         fdt_fixup_nor_flash_size(blob);
 427 #endif
 428         ft_adapt_flash_base(blob);
 429 #endif
 430         /* fix up the phy address */
 431         do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
 432 }
 433 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */