board/ebony/ebony.c

   1 /*
   2  *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23
  24 #include <common.h>
  25 #include "ebony.h"
  26 #include <asm/processor.h>
  27 #include <spd_sdram.h>
  28
  29 #define BOOT_SMALL_FLASH        32      /* 00100000 */
  30 #define FLASH_ONBD_N            2       /* 00000010 */
  31 #define FLASH_SRAM_SEL          1       /* 00000001 */
  32
  33 long int fixed_sdram (void);
  34
  35 int board_early_init_f (void)
  36 {
  37         uint reg;
  38         unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
  39         unsigned char status;
  40
  41
  42         /*--------------------------------------------------------------------
  43          * Setup the external bus controller/chip selects
  44          *-------------------------------------------------------------------*/
  45         mtdcr (ebccfga, xbcfg);
  46         reg = mfdcr (ebccfgd);
  47         mtdcr (ebccfgd, reg | 0x04000000);      /* Set ATC */
  48
  49         mtebc (pb1ap, 0x02815480);      /* NVRAM/RTC */
  50         mtebc (pb1cr, 0x48018000);      /* BA=0x480 1MB R/W 8-bit */
  51         mtebc (pb7ap, 0x01015280);      /* FPGA registers */
  52         mtebc (pb7cr, 0x48318000);      /* BA=0x483 1MB R/W 8-bit */
  53
  54         /* read FPGA_REG0  and set the bus controller */
  55         status = *fpga_base;
  56         if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
  57                 mtebc (pb0ap, 0x9b015480);      /* FLASH/SRAM */
  58                 mtebc (pb0cr, 0xfff18000);      /* BAS=0xfff 1MB R/W 8-bit */
  59                 mtebc (pb2ap, 0x9b015480);      /* 4MB FLASH */
  60                 mtebc (pb2cr, 0xff858000);      /* BAS=0xff8 4MB R/W 8-bit */
  61         } else {
  62                 mtebc (pb0ap, 0x9b015480);      /* 4MB FLASH */
  63                 mtebc (pb0cr, 0xffc58000);      /* BAS=0xffc 4MB R/W 8-bit */
  64
  65                 /* set CS2 if FLASH_ONBD_N == 0 */
  66                 if (!(status & FLASH_ONBD_N)) {
  67                         mtebc (pb2ap, 0x9b015480);      /* FLASH/SRAM */
  68                         mtebc (pb2cr, 0xff818000);      /* BAS=0xff8 4MB R/W 8-bit */
  69                 }
  70         }
  71
  72         /*--------------------------------------------------------------------
  73          * Setup the interrupt controller polarities, triggers, etc.
  74          *-------------------------------------------------------------------*/
  75         mtdcr (uic0sr, 0xffffffff);     /* clear all */
  76         mtdcr (uic0er, 0x00000000);     /* disable all */
  77         mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
  78         mtdcr (uic0pr, 0xfffffe13);     /* per ref-board manual */
  79         mtdcr (uic0tr, 0x01c00008);     /* per ref-board manual */
  80         mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
  81         mtdcr (uic0sr, 0xffffffff);     /* clear all */
  82
  83         mtdcr (uic1sr, 0xffffffff);     /* clear all */
  84         mtdcr (uic1er, 0x00000000);     /* disable all */
  85         mtdcr (uic1cr, 0x00000000);     /* all non-critical */
  86         mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
  87         mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
  88         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
  89         mtdcr (uic1sr, 0xffffffff);     /* clear all */
  90
  91         return 0;
  92 }
  93
  94
  95 int checkboard (void)
  96 {
  97         sys_info_t sysinfo;
  98
  99         get_sys_info (&sysinfo);
 100
 101         printf ("Board: IBM 440GP Evaluation Board (Ebony)\n");
 102         printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
 103         printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 104         printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
 105         printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
 106         printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
 107         return (0);
 108 }
 109
 110
 111 long int initdram (int board_type)
 112 {
 113         long dram_size = 0;
 114
 115 #if defined(CONFIG_SPD_EEPROM)
 116         dram_size = spd_sdram (0);
 117 #else
 118         dram_size = fixed_sdram ();
 119 #endif
 120         return dram_size;
 121 }
 122
 123
 124 #if defined(CFG_DRAM_TEST)
 125 int testdram (void)
 126 {
 127         uint *pstart = (uint *) 0x00000000;
 128         uint *pend = (uint *) 0x08000000;
 129         uint *p;
 130
 131         for (p = pstart; p < pend; p++)
 132                 *p = 0xaaaaaaaa;
 133
 134         for (p = pstart; p < pend; p++) {
 135                 if (*p != 0xaaaaaaaa) {
 136                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 137                         return 1;
 138                 }
 139         }
 140
 141         for (p = pstart; p < pend; p++)
 142                 *p = 0x55555555;
 143
 144         for (p = pstart; p < pend; p++) {
 145                 if (*p != 0x55555555) {
 146                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 147                         return 1;
 148                 }
 149         }
 150         return 0;
 151 }
 152 #endif
 153
 154 #if !defined(CONFIG_SPD_EEPROM)
 155 /*************************************************************************
 156  *  fixed sdram init -- doesn't use serial presence detect.
 157  *
 158  *  Assumes:    128 MB, non-ECC, non-registered
 159  *              PLB @ 133 MHz
 160  *
 161  ************************************************************************/
 162 long int fixed_sdram (void)
 163 {
 164         uint reg;
 165
 166         /*--------------------------------------------------------------------
 167          * Setup some default
 168          *------------------------------------------------------------------*/
 169         mtsdram (mem_uabba, 0x00000000);        /* ubba=0 (default)             */
 170         mtsdram (mem_slio, 0x00000000);         /* rdre=0 wrre=0 rarw=0         */
 171         mtsdram (mem_devopt, 0x00000000);       /* dll=0 ds=0 (normal)          */
 172         mtsdram (mem_wddctr, 0x00000000);       /* wrcp=0 dcd=0                 */
 173         mtsdram (mem_clktr, 0x40000000);        /* clkp=1 (90 deg wr) dcdt=0    */
 174
 175         /*--------------------------------------------------------------------
 176          * Setup for board-specific specific mem
 177          *------------------------------------------------------------------*/
 178         /*
 179          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 180          */
 181         mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
 182         mtsdram (mem_tr0, 0x410a4012);  /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 183         /* RA=10 RD=3                       */
 184         mtsdram (mem_tr1, 0x8080082f);  /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
 185         mtsdram (mem_rtr, 0x08200000);  /* Rate 15.625 ns @ 133 MHz PLB     */
 186         mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
 187         udelay (400);                   /* Delay 200 usecs (min)            */
 188
 189         /*--------------------------------------------------------------------
 190          * Enable the controller, then wait for DCEN to complete
 191          *------------------------------------------------------------------*/
 192         mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit           */
 193         for (;;) {
 194                 mfsdram (mem_mcsts, reg);
 195                 if (reg & 0x80000000)
 196                         break;
 197         }
 198
 199         return (128 * 1024 * 1024);     /* 128 MB                           */
 200 }
 201 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 202
 203
 204 /*************************************************************************
 205  *  pci_pre_init
 206  *
 207  *  This routine is called just prior to registering the hose and gives
 208  *  the board the opportunity to check things. Returning a value of zero
 209  *  indicates that things are bad & PCI initialization should be aborted.
 210  *
 211  *      Different boards may wish to customize the pci controller structure
 212  *      (add regions, override default access routines, etc) or perform
 213  *      certain pre-initialization actions.
 214  *
 215  ************************************************************************/
 216 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 217 int pci_pre_init(struct pci_controller * hose )
 218 {
 219     unsigned long strap;
 220
 221         /*--------------------------------------------------------------------------+
 222      *  The ebony board is always configured as the host & requires the
 223      *  PCI arbiter to be enabled.
 224          *--------------------------------------------------------------------------*/
 225     strap = mfdcr(cpc0_strp1);
 226     if( (strap & 0x00100000) == 0 ){
 227         printf("PCI: CPC0_STRP1[PAE] not set.\n");
 228         return 0;
 229     }
 230
 231     return 1;
 232 }
 233 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 234
 235 /*************************************************************************
 236  *  pci_target_init
 237  *
 238  *      The bootstrap configuration provides default settings for the pci
 239  *      inbound map (PIM). But the bootstrap config choices are limited and
 240  *      may not be sufficient for a given board.
 241  *
 242  ************************************************************************/
 243 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 244 void pci_target_init(struct pci_controller * hose )
 245 {
 246         DECLARE_GLOBAL_DATA_PTR;
 247
 248         /*--------------------------------------------------------------------------+
 249          * Disable everything
 250          *--------------------------------------------------------------------------*/
 251         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 252         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 253         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 254         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 255
 256         /*--------------------------------------------------------------------------+
 257          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 258      * options to not support sizes such as 128/256 MB.
 259          *--------------------------------------------------------------------------*/
 260         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 261         out32r( PCIX0_PIM0LAH, 0 );
 262         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 263
 264         out32r( PCIX0_BAR0, 0 );
 265
 266         /*--------------------------------------------------------------------------+
 267          * Program the board's subsystem id/vendor id
 268          *--------------------------------------------------------------------------*/
 269     out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 270     out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 271
 272         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 273 }
 274 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 275
 276
 277 /*************************************************************************
 278  *  is_pci_host
 279  *
 280  *      This routine is called to determine if a pci scan should be
 281  *      performed. With various hardware environments (especially cPCI and
 282  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 283  *      bit in the strap register, or generic host/adapter assumptions.
 284  *
 285  *      Rather than hard-code a bad assumption in the general 440 code, the
 286  *      440 pci code requires the board to decide at runtime.
 287  *
 288  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 289  *
 290  *
 291  ************************************************************************/
 292 #if defined(CONFIG_PCI)
 293 int is_pci_host(struct pci_controller *hose)
 294 {
 295     /* The ebony board is always configured as host. */
 296     return(1);
 297 }
 298 #endif /* defined(CONFIG_PCI) */