board/edb93xx/sdram_cfg.c

   1 /*
   2  * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
   3  *
   4  * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <asm/io.h>
  26 #include "sdram_cfg.h"
  27 #include "early_udelay.h"
  28
  29 #define PROGRAM_MODE_REG(bank)          (*(volatile uint32_t *)         \
  30                 (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
  31
  32 #define PRECHARGE_BANK(bank)            (*(volatile uint32_t *)         \
  33                 (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0
  34
  35 static void precharge_all_banks(void);
  36 static void setup_refresh_timer(void);
  37 static void program_mode_registers(void);
  38
  39 void sdram_cfg(void)
  40 {
  41         struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
  42
  43         writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
  44
  45         /* Issue continous NOP commands */
  46         writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
  47
  48         early_udelay(200);
  49
  50         precharge_all_banks();
  51
  52         setup_refresh_timer();
  53
  54         program_mode_registers();
  55
  56         /* Select normal operation mode */
  57         writel(GLCONFIG_CKE, &sdram->glconfig);
  58 }
  59
  60 static void precharge_all_banks(void)
  61 {
  62         struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
  63
  64         /* Issue PRECHARGE ALL commands */
  65         writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig);
  66
  67         /*
  68          * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always
  69          * issued
  70          *
  71          * Cirrus proposes a workaround which consists in performing a read from
  72          * each bank to force the precharge. This causes some boards to hang.
  73          * Writing to the SDRAM banks instead of reading has the same
  74          * side-effect (the SDRAM controller issues the necessary precharges),
  75          * but is known to work on all supported boards
  76          */
  77
  78         PRECHARGE_BANK(0);
  79
  80 #if (CONFIG_NR_DRAM_BANKS >= 2)
  81         PRECHARGE_BANK(1);
  82 #endif
  83
  84 #if (CONFIG_NR_DRAM_BANKS >= 3)
  85         PRECHARGE_BANK(2);
  86 #endif
  87
  88 #if (CONFIG_NR_DRAM_BANKS == 4)
  89         PRECHARGE_BANK(3);
  90 #endif
  91 }
  92
  93 static void setup_refresh_timer(void)
  94 {
  95         struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
  96
  97         /* Load refresh timer with 10 to issue refresh every 10 cycles */
  98         writel(0x0a, &sdram->refrshtimr);
  99
 100         /*
 101          * Wait at least 80 clock cycles to provide 8 refresh cycles
 102          * to all SDRAMs
 103          */
 104         early_udelay(1);
 105
 106         /*
 107          * Program refresh timer with normal value
 108          * We need 8192 refresh cycles every 64ms
 109          * at 15ns (HCLK >= 66MHz) per cycle:
 110          * 64ms / 8192 = 7.8125us
 111          * 7.8125us / 15ns = 520 (0x208)
 112          */
 113         /*
 114          * TODO: redboot uses 0x1e0 for the slowest possible device
 115          * but i don't understand how this value is calculated
 116          */
 117         writel(0x208, &sdram->refrshtimr);
 118 }
 119
 120 static void program_mode_registers(void)
 121 {
 122         struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
 123
 124         /* Select mode register update mode */
 125         writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
 126
 127         /*
 128          * The mode registers are programmed by performing a read from each
 129          * SDRAM bank. The value of the address that is read defines the value
 130          * that is written into the mode register
 131          */
 132
 133         PROGRAM_MODE_REG(0);
 134
 135 #if (CONFIG_NR_DRAM_BANKS >= 2)
 136         PROGRAM_MODE_REG(1);
 137 #endif
 138
 139 #if (CONFIG_NR_DRAM_BANKS >= 3)
 140         PROGRAM_MODE_REG(2);
 141 #endif
 142
 143 #if (CONFIG_NR_DRAM_BANKS == 4)
 144         PROGRAM_MODE_REG(3);
 145 #endif
 146 }