1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Stefano Babic <sbabic@denx.de>
5 * Based on other i.MX6 boards
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <linux/errno.h>
14 #include <asm/mach-imx/mxc_i2c.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/video.h>
19 #include <fsl_esdhc_imx.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h>
25 #include <asm/arch/sys_proto.h>
28 #include <power/pmic.h>
29 #include <power/pfuze100_pmic.h>
30 #include <asm/arch/mx6-ddr.h>
32 DECLARE_GLOBAL_DATA_PTR
;
34 #define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12))
36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
50 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
53 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
54 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
56 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
58 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
62 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
64 #define ETH_PHY_RESET IMX_GPIO_NR(2, 4)
68 gd
->ram_size
= imx_ddr_size();
73 iomux_v3_cfg_t
const uart2_pads
[] = {
74 MX6_PAD_SD3_DAT5__UART2_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
75 MX6_PAD_SD3_DAT4__UART2_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
78 static void setup_iomux_uart(void)
80 imx_iomux_v3_setup_multiple_pads(uart2_pads
, ARRAY_SIZE(uart2_pads
));
83 #ifdef CONFIG_TARGET_ZC5202
84 iomux_v3_cfg_t
const enet_pads
[] = {
85 MX6_PAD_GPIO_18__ENET_RX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
86 MX6_PAD_ENET_RXD0__ENET_RX_DATA0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
87 MX6_PAD_ENET_RXD1__ENET_RX_DATA1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
88 MX6_PAD_KEY_COL2__ENET_RX_DATA2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
89 MX6_PAD_KEY_COL0__ENET_RX_DATA3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
90 MX6_PAD_ENET_CRS_DV__ENET_RX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
91 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL_CLK
),
92 MX6_PAD_ENET_TXD0__ENET_TX_DATA0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
93 MX6_PAD_ENET_TXD1__ENET_TX_DATA1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
94 MX6_PAD_GPIO_19__ENET_TX_ER
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
95 MX6_PAD_KEY_ROW2__ENET_TX_DATA2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
96 MX6_PAD_KEY_ROW0__ENET_TX_DATA3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
97 MX6_PAD_ENET_TX_EN__ENET_TX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
98 MX6_PAD_ENET_RX_ER__ENET_RX_ER
| MUX_PAD_CTRL(ENET_PAD_CTRL_PD
),
100 MX6_PAD_NANDF_D4__GPIO2_IO04
| MUX_PAD_CTRL(ENET_PAD_CTRL_PD
),
101 /* Switch Interrupt */
102 MX6_PAD_NANDF_D5__GPIO2_IO05
| MUX_PAD_CTRL(NO_PAD_CTRL
),
103 /* use CRS and COL pads as GPIOs */
104 MX6_PAD_KEY_COL3__GPIO4_IO12
| MUX_PAD_CTRL(OPEN_PAD_CTRL
),
105 MX6_PAD_KEY_ROW1__GPIO4_IO09
| MUX_PAD_CTRL(OPEN_PAD_CTRL
),
109 #define BOARD_NAME "EL6x-ZC5202"
111 iomux_v3_cfg_t
const enet_pads
[] = {
112 MX6_PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
113 MX6_PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
114 MX6_PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
115 MX6_PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
116 MX6_PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
117 MX6_PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
118 MX6_PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
119 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
120 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL_CLK
),
121 MX6_PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
122 MX6_PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
123 MX6_PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
124 MX6_PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
125 MX6_PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
126 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
127 MX6_PAD_NANDF_D4__GPIO2_IO04
| MUX_PAD_CTRL(NO_PAD_CTRL
),
128 MX6_PAD_NANDF_D5__GPIO2_IO05
| MUX_PAD_CTRL(NO_PAD_CTRL
),
130 #define BOARD_NAME "EL6x-ZC5601"
133 static void setup_iomux_enet(void)
135 imx_iomux_v3_setup_multiple_pads(enet_pads
, ARRAY_SIZE(enet_pads
));
137 #ifdef CONFIG_TARGET_ZC5202
138 /* set CRS and COL to input */
139 gpio_direction_input(IMX_GPIO_NR(4, 9));
140 gpio_direction_input(IMX_GPIO_NR(4, 12));
143 gpio_direction_output(ETH_PHY_RESET
, 0);
145 gpio_set_value(ETH_PHY_RESET
, 1);
149 int board_phy_config(struct phy_device
*phydev
)
151 if (phydev
->drv
->config
)
152 phydev
->drv
->config(phydev
);
157 #ifdef CONFIG_MXC_SPI
158 #ifdef CONFIG_TARGET_ZC5202
159 iomux_v3_cfg_t
const ecspi1_pads
[] = {
160 MX6_PAD_DISP0_DAT20__ECSPI1_SCLK
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
161 MX6_PAD_DISP0_DAT21__ECSPI1_MOSI
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
162 MX6_PAD_DISP0_DAT22__ECSPI1_MISO
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
163 MX6_PAD_DISP0_DAT23__GPIO5_IO17
| MUX_PAD_CTRL(NO_PAD_CTRL
),
164 MX6_PAD_DISP0_DAT15__GPIO5_IO09
| MUX_PAD_CTRL(NO_PAD_CTRL
),
167 iomux_v3_cfg_t
const ecspi3_pads
[] = {
168 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
169 MX6_PAD_DISP0_DAT2__ECSPI3_MISO
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
170 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
171 MX6_PAD_DISP0_DAT7__GPIO4_IO28
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
172 MX6_PAD_DISP0_DAT8__GPIO4_IO29
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
173 MX6_PAD_DISP0_DAT9__GPIO4_IO30
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
174 MX6_PAD_DISP0_DAT10__GPIO4_IO31
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
178 iomux_v3_cfg_t
const ecspi4_pads
[] = {
179 MX6_PAD_EIM_D21__ECSPI4_SCLK
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
180 MX6_PAD_EIM_D28__ECSPI4_MOSI
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
181 MX6_PAD_EIM_D22__ECSPI4_MISO
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
182 MX6_PAD_EIM_D20__GPIO3_IO20
| MUX_PAD_CTRL(NO_PAD_CTRL
),
185 int board_spi_cs_gpio(unsigned bus
, unsigned cs
)
187 return (bus
== CONFIG_SF_DEFAULT_BUS
&& cs
== CONFIG_SF_DEFAULT_CS
)
188 ? (IMX_GPIO_NR(3, 20)) : -1;
191 static void setup_spi(void)
193 #ifdef CONFIG_TARGET_ZC5202
194 gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
195 gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
196 gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
197 gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
198 imx_iomux_v3_setup_multiple_pads(ecspi1_pads
, ARRAY_SIZE(ecspi1_pads
));
201 gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
202 gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
203 imx_iomux_v3_setup_multiple_pads(ecspi4_pads
, ARRAY_SIZE(ecspi4_pads
));
205 enable_spi_clk(true, 3);
209 static struct i2c_pads_info i2c_pad_info1
= {
211 .i2c_mode
= MX6_PAD_EIM_EB2__I2C2_SCL
| I2C_PAD
,
212 .gpio_mode
= MX6_PAD_EIM_EB2__GPIO2_IO30
| I2C_PAD
,
213 .gp
= IMX_GPIO_NR(2, 30)
216 .i2c_mode
= MX6_PAD_KEY_ROW3__I2C2_SDA
| I2C_PAD
,
217 .gpio_mode
= MX6_PAD_KEY_ROW3__GPIO4_IO13
| I2C_PAD
,
218 .gp
= IMX_GPIO_NR(4, 13)
222 static struct i2c_pads_info i2c_pad_info2
= {
224 .i2c_mode
= MX6_PAD_GPIO_5__I2C3_SCL
| I2C_PAD
,
225 .gpio_mode
= MX6_PAD_GPIO_5__GPIO1_IO05
| I2C_PAD
,
226 .gp
= IMX_GPIO_NR(1, 5)
229 .i2c_mode
= MX6_PAD_GPIO_16__I2C3_SDA
| I2C_PAD
,
230 .gpio_mode
= MX6_PAD_GPIO_16__GPIO7_IO11
| I2C_PAD
,
231 .gp
= IMX_GPIO_NR(7, 11)
235 iomux_v3_cfg_t
const usdhc2_pads
[] = {
236 MX6_PAD_SD2_CLK__SD2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
237 MX6_PAD_SD2_CMD__SD2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
238 MX6_PAD_SD2_DAT0__SD2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
239 MX6_PAD_SD2_DAT1__SD2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
240 MX6_PAD_SD2_DAT2__SD2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
241 MX6_PAD_SD2_DAT3__SD2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
242 MX6_PAD_GPIO_4__SD2_CD_B
| MUX_PAD_CTRL(NO_PAD_CTRL
), /* CD */
245 iomux_v3_cfg_t
const usdhc4_pads
[] = {
246 MX6_PAD_SD4_CLK__SD4_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
247 MX6_PAD_SD4_CMD__SD4_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
248 MX6_PAD_SD4_DAT0__SD4_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
249 MX6_PAD_SD4_DAT1__SD4_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
250 MX6_PAD_SD4_DAT2__SD4_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
251 MX6_PAD_SD4_DAT3__SD4_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
252 MX6_PAD_SD4_DAT4__SD4_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
253 MX6_PAD_SD4_DAT5__SD4_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
254 MX6_PAD_SD4_DAT6__SD4_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
255 MX6_PAD_SD4_DAT7__SD4_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
258 #ifdef CONFIG_FSL_ESDHC_IMX
259 struct fsl_esdhc_cfg usdhc_cfg
[2] = {
264 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
266 int board_mmc_getcd(struct mmc
*mmc
)
268 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
271 switch (cfg
->esdhc_base
) {
272 case USDHC2_BASE_ADDR
:
273 ret
= !gpio_get_value(USDHC2_CD_GPIO
);
275 case USDHC4_BASE_ADDR
:
276 ret
= 1; /* eMMC/uSDHC4 is always present */
283 int board_mmc_init(bd_t
*bis
)
285 #ifndef CONFIG_SPL_BUILD
290 * According to the board_mmc_init() the following map is done:
291 * (U-boot device node) (Physical Port)
296 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
299 imx_iomux_v3_setup_multiple_pads(
300 usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
301 gpio_direction_input(USDHC2_CD_GPIO
);
302 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
305 imx_iomux_v3_setup_multiple_pads(
306 usdhc4_pads
, ARRAY_SIZE(usdhc4_pads
));
307 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC4_CLK
);
310 printf("Warning: you configured more USDHC controllers"
311 "(%d) then supported by the board (%d)\n",
312 i
+ 1, CONFIG_SYS_FSL_USDHC_NUM
);
316 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
323 struct src
*psrc
= (struct src
*)SRC_BASE_ADDR
;
324 unsigned reg
= readl(&psrc
->sbmr1
) >> 11;
327 * Upon reading BOOT_CFG register the following map is done:
328 * Bit 11 and 12 of BOOT_CFG register can determine the current
337 imx_iomux_v3_setup_multiple_pads(
338 usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
339 usdhc_cfg
[0].esdhc_base
= USDHC2_BASE_ADDR
;
340 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
341 gd
->arch
.sdhc_clk
= usdhc_cfg
[0].sdhc_clk
;
344 imx_iomux_v3_setup_multiple_pads(
345 usdhc4_pads
, ARRAY_SIZE(usdhc4_pads
));
346 usdhc_cfg
[0].esdhc_base
= USDHC4_BASE_ADDR
;
347 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC4_CLK
);
348 gd
->arch
.sdhc_clk
= usdhc_cfg
[0].sdhc_clk
;
352 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[0]);
360 * Do not overwrite the console
361 * Use always serial for U-Boot console
363 int overwrite_console(void)
368 int board_eth_init(bd_t
*bis
)
373 return cpu_eth_init(bis
);
376 int board_early_init_f(void)
387 /* address of boot parameters */
388 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
390 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info1
);
391 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info2
);
396 int power_init_board(void)
402 ret
= power_pfuze100_init(I2C_PMIC
);
406 p
= pmic_get("PFUZE100");
411 pmic_reg_read(p
, PFUZE100_DEVICEID
, ®
);
412 printf("PMIC: PFUZE100 ID=0x%02x\n", reg
);
414 /* Increase VGEN3 from 2.5 to 2.8V */
415 pmic_reg_read(p
, PFUZE100_VGEN3VOL
, ®
);
416 reg
&= ~LDO_VOL_MASK
;
418 pmic_reg_write(p
, PFUZE100_VGEN3VOL
, reg
);
420 /* Increase VGEN5 from 2.8 to 3V */
421 pmic_reg_read(p
, PFUZE100_VGEN5VOL
, ®
);
422 reg
&= ~LDO_VOL_MASK
;
424 pmic_reg_write(p
, PFUZE100_VGEN5VOL
, reg
);
426 /* Set SW1AB stanby volage to 0.975V */
427 pmic_reg_read(p
, PFUZE100_SW1ABSTBY
, ®
);
428 reg
&= ~SW1x_STBY_MASK
;
430 pmic_reg_write(p
, PFUZE100_SW1ABSTBY
, reg
);
432 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
433 pmic_reg_read(p
, PFUZE100_SW1ABCONF
, ®
);
434 reg
&= ~SW1xCONF_DVSSPEED_MASK
;
435 reg
|= SW1xCONF_DVSSPEED_4US
;
436 pmic_reg_write(p
, PFUZE100_SW1ABCONF
, reg
);
438 /* Set SW1C standby voltage to 0.975V */
439 pmic_reg_read(p
, PFUZE100_SW1CSTBY
, ®
);
440 reg
&= ~SW1x_STBY_MASK
;
442 pmic_reg_write(p
, PFUZE100_SW1CSTBY
, reg
);
444 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
445 pmic_reg_read(p
, PFUZE100_SW1CCONF
, ®
);
446 reg
&= ~SW1xCONF_DVSSPEED_MASK
;
447 reg
|= SW1xCONF_DVSSPEED_4US
;
448 pmic_reg_write(p
, PFUZE100_SW1CCONF
, reg
);
453 #ifdef CONFIG_CMD_BMODE
454 static const struct boot_mode board_boot_modes
[] = {
455 /* 4 bit bus width */
456 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
457 /* 8 bit bus width */
458 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
463 int board_late_init(void)
465 #ifdef CONFIG_CMD_BMODE
466 add_board_boot_modes(board_boot_modes
);
469 env_set("board_name", BOARD_NAME
);
476 puts(BOARD_NAME
"\n");
481 #ifdef CONFIG_SPL_BUILD
483 #include <linux/libfdt.h>
485 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs
= {
486 .dram_sdclk_0
= 0x00020030,
487 .dram_sdclk_1
= 0x00020030,
488 .dram_cas
= 0x00020030,
489 .dram_ras
= 0x00020030,
490 .dram_reset
= 0x00020030,
491 .dram_sdcke0
= 0x00003000,
492 .dram_sdcke1
= 0x00003000,
493 .dram_sdba2
= 0x00000000,
494 .dram_sdodt0
= 0x00003030,
495 .dram_sdodt1
= 0x00003030,
496 .dram_sdqs0
= 0x00000030,
497 .dram_sdqs1
= 0x00000030,
498 .dram_sdqs2
= 0x00000030,
499 .dram_sdqs3
= 0x00000030,
500 .dram_sdqs4
= 0x00000030,
501 .dram_sdqs5
= 0x00000030,
502 .dram_sdqs6
= 0x00000030,
503 .dram_sdqs7
= 0x00000030,
504 .dram_dqm0
= 0x00020030,
505 .dram_dqm1
= 0x00020030,
506 .dram_dqm2
= 0x00020030,
507 .dram_dqm3
= 0x00020030,
508 .dram_dqm4
= 0x00020030,
509 .dram_dqm5
= 0x00020030,
510 .dram_dqm6
= 0x00020030,
511 .dram_dqm7
= 0x00020030,
514 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs
= {
515 .grp_ddr_type
= 0x000C0000,
516 .grp_ddrmode_ctl
= 0x00020000,
517 .grp_ddrpke
= 0x00000000,
518 .grp_addds
= 0x00000030,
519 .grp_ctlds
= 0x00000030,
520 .grp_ddrmode
= 0x00020000,
521 .grp_b0ds
= 0x00000030,
522 .grp_b1ds
= 0x00000030,
523 .grp_b2ds
= 0x00000030,
524 .grp_b3ds
= 0x00000030,
525 .grp_b4ds
= 0x00000030,
526 .grp_b5ds
= 0x00000030,
527 .grp_b6ds
= 0x00000030,
528 .grp_b7ds
= 0x00000030,
531 const struct mx6_mmdc_calibration mx6_mmcd_calib
= {
532 .p0_mpwldectrl0
= 0x001F001F,
533 .p0_mpwldectrl1
= 0x001F001F,
534 .p1_mpwldectrl0
= 0x00440044,
535 .p1_mpwldectrl1
= 0x00440044,
536 .p0_mpdgctrl0
= 0x434B0350,
537 .p0_mpdgctrl1
= 0x034C0359,
538 .p1_mpdgctrl0
= 0x434B0350,
539 .p1_mpdgctrl1
= 0x03650348,
540 .p0_mprddlctl
= 0x4436383B,
541 .p1_mprddlctl
= 0x39393341,
542 .p0_mpwrdlctl
= 0x35373933,
543 .p1_mpwrdlctl
= 0x48254A36,
546 /* MT41K128M16JT-125 */
547 static struct mx6_ddr3_cfg mem_ddr
= {
560 static void ccgr_init(void)
562 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
564 writel(0x00C03F3F, &ccm
->CCGR0
);
565 writel(0x0030FC03, &ccm
->CCGR1
);
566 writel(0x0FFFC000, &ccm
->CCGR2
);
567 writel(0x3FF00000, &ccm
->CCGR3
);
568 writel(0x00FFF300, &ccm
->CCGR4
);
569 writel(0x0F0000C3, &ccm
->CCGR5
);
570 writel(0x000003FF, &ccm
->CCGR6
);
574 * This section requires the differentiation between iMX6 Sabre boards, but
575 * for now, it will configure only for the mx6q variant.
577 static void spl_dram_init(void)
579 struct mx6_ddr_sysinfo sysinfo
= {
580 /* width of data bus:0=16,1=32,2=64 */
582 /* config for full 4GB range so that get_mem_size() works */
583 .cs_density
= 32, /* 32Gb per CS */
584 /* single chip select */
587 .rtt_wr
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
588 .rtt_nom
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
589 .walat
= 1, /* Write additional latency */
590 .ralat
= 5, /* Read additional latency */
591 .mif3_mode
= 3, /* Command prediction working mode */
592 .bi_on
= 1, /* Bank interleaving enabled */
593 .sde_to_rst
= 0x10, /* 14 cycles, 200us (JEDEC default) */
594 .rst_to_cke
= 0x23, /* 33 cycles, 500us (JEDEC default) */
595 .ddr_type
= DDR_TYPE_DDR3
,
596 .refsel
= 1, /* Refresh cycles at 32KHz */
597 .refr
= 7, /* 8 refresh commands per refresh cycle */
600 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs
, &mx6_grp_ioregs
);
601 mx6_dram_cfg(&sysinfo
, &mx6_mmcd_calib
, &mem_ddr
);
604 void board_init_f(ulong dummy
)
606 /* setup AIPS and disable watchdog */
612 /* iomux and setup of i2c */
613 board_early_init_f();
618 /* UART clocks enabled and gd valid - init serial console */
619 preloader_console_init();
621 /* DDR initialization */
625 memset(__bss_start
, 0, __bss_end
- __bss_start
);
627 /* load/boot image from boot device */
628 board_init_r(NULL
, 0);