board/eltec/bab7xx/l2cache.c

   1 /*
   2  * (C) Copyright 2002 ELTEC Elektronik AG
   3  * Frank Gottschling <fgottschling@eltec.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 #if defined(CFG_L2_BAB7xx)
  27
  28 #include <pci.h>
  29 #include <mpc106.h>
  30
  31 /* defines L2CR register for MPC750 */
  32
  33 #define L2CR_E           0x80000000
  34 #define L2CR_256K        0x10000000
  35 #define L2CR_512K        0x20000000
  36 #define L2CR_1024K       0x30000000
  37 #define L2CR_I           0x00200000
  38 #define L2CR_SL          0x00008000
  39 #define L2CR_IP          0x00000001
  40
  41 /*----------------------------------------------------------------------------*/
  42
  43 static int dummy (int dummy)
  44 {
  45     return (dummy+1);
  46 }
  47
  48 /*----------------------------------------------------------------------------*/
  49
  50 int l2_cache_enable (int l2control)
  51 {
  52     if (l2control)              /* BAB750 */
  53     {
  54         mtspr(SPRN_L2CR, l2control);
  55         mtspr(SPRN_L2CR, (l2control | L2CR_I));
  56         while (mfspr(SPRN_L2CR) & L2CR_IP)
  57             ;
  58         mtspr(SPRN_L2CR, (l2control | L2CR_E));
  59         return (0);
  60     }
  61     else /* BAB740 */
  62     {
  63         int picr1, picr2, mask;
  64         int picr2CacheSize, cacheSize;
  65         int *d;
  66         int devbusfn;
  67         u32 reg32;
  68
  69         devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA,
  70                                    PCI_DEVICE_ID_MOTOROLA_MPC106, 0);
  71         if (devbusfn == -1)
  72             return (-1);
  73
  74         pci_read_config_dword  (devbusfn, PCI_PICR2, &reg32);
  75         reg32 &= ~PICR2_L2_EN;
  76         pci_write_config_dword (devbusfn, PCI_PICR2, reg32);
  77
  78         /* cache size */
  79         if (*(volatile unsigned char *) (CFG_ISA_IO + 0x220) & 0x04)
  80         {
  81             /* cache size is 512 KB */
  82             picr2CacheSize = PICR2_L2_SIZE_512K;
  83             cacheSize = 0x80000;
  84         }
  85         else
  86         {
  87             /* cache size is 256 KB */
  88             picr2CacheSize = PICR2_L2_SIZE_256K;
  89             cacheSize = 0x40000;
  90         }
  91
  92         /* setup PICR1 */
  93         mask =
  94         ~(PICR1_CF_BREAD_WS(1) |
  95           PICR1_CF_BREAD_WS(2) |
  96           PICR1_CF_CBA(0xff) |
  97           PICR1_CF_CACHE_1G |
  98           PICR1_CF_DPARK |
  99           PICR1_CF_APARK |
 100           PICR1_CF_L2_CACHE_MASK);
 101
 102         picr1 =
 103         (PICR1_CF_CBA(0x3f) |
 104          PICR1_CF_CACHE_1G |
 105          PICR1_CF_APARK |
 106          PICR1_CF_DPARK |
 107          PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */
 108
 109         pci_read_config_dword  (devbusfn, PCI_PICR1, &reg32);
 110         reg32 &= mask;
 111         reg32 |= picr1;
 112         pci_write_config_dword (devbusfn, PCI_PICR1, reg32);
 113
 114         /*
 115          * invalidate all L2 cache
 116          */
 117         picr2 =
 118         (PICR2_CF_INV_MODE |
 119          PICR2_CF_HIT_HIGH |
 120          PICR2_CF_MOD_HIGH |
 121          PICR2_CF_L2_HIT_DELAY(1) |
 122          PICR2_CF_APHASE_WS(1) |
 123          picr2CacheSize);
 124
 125         pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
 126
 127         /*
 128          * dummy transactions
 129          */
 130         for (d=0; d<(int *)(2*cacheSize); d++)
 131             dummy(*d);
 132
 133         pci_write_config_dword (devbusfn, PCI_PICR2,
 134                                 (picr2 | PICR2_CF_FLUSH_L2));
 135
 136         /* setup PICR2 */
 137         picr2 =
 138         (PICR2_CF_FAST_CASTOUT |
 139          PICR2_CF_WDATA |
 140          PICR2_CF_ADDR_ONLY_DISABLE |
 141          PICR2_CF_HIT_HIGH |
 142          PICR2_CF_MOD_HIGH |
 143          PICR2_L2_UPDATE_EN |
 144          PICR2_L2_EN |
 145          PICR2_CF_APHASE_WS(1) |
 146          PICR2_CF_DATA_RAM_PBURST |
 147          PICR2_CF_L2_HIT_DELAY(1) |
 148          PICR2_CF_SNOOP_WS(2) |
 149          picr2CacheSize);
 150
 151         pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
 152     }
 153     return (0);
 154 }
 155
 156 /*----------------------------------------------------------------------------*/
 157
 158 #endif /* (CFG_L2_BAB7xx) */
 159