2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/sizes.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/imx-common/iomux-v3.h>
22 #include <asm/imx-common/video.h>
24 DECLARE_GLOBAL_DATA_PTR
;
26 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
28 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
30 static iomux_v3_cfg_t
const uart4_pads
[] = {
31 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
32 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
35 #ifdef CONFIG_NAND_MXS
37 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
38 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
40 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
42 iomux_v3_cfg_t gpmi_pads
[] = {
43 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
44 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
45 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
46 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL0
)),
47 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
48 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
49 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
50 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
51 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
52 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
53 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
54 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
55 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
56 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
57 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
60 static void setup_gpmi_nand(void)
62 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
64 /* config gpmi nand iomux */
65 SETUP_IOMUX_PADS(gpmi_pads
);
67 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
68 clrbits_le32(&mxc_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
70 /* config gpmi and bch clock to 100 MHz */
71 clrsetbits_le32(&mxc_ccm
->cs2cdr
,
72 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK
|
73 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK
|
74 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK
,
75 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
76 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
77 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
79 /* enable ENFC_CLK_ROOT clock */
80 setbits_le32(&mxc_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
82 /* enable gpmi and bch clock gating */
83 setbits_le32(&mxc_ccm
->CCGR4
,
84 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
85 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
86 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
87 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
88 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET
);
90 /* enable apbh clock gating */
91 setbits_le32(&mxc_ccm
->CCGR0
, MXC_CCM_CCGR0_APBHDMA_MASK
);
95 #if defined(CONFIG_VIDEO_IPUV3)
96 static iomux_v3_cfg_t
const rgb_pads
[] = {
97 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK
),
98 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15
),
99 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02
),
100 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03
),
101 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00
),
102 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01
),
103 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02
),
104 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03
),
105 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04
),
106 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05
),
107 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06
),
108 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07
),
109 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08
),
110 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09
),
111 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10
),
112 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11
),
113 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12
),
114 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13
),
115 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14
),
116 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15
),
117 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16
),
118 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17
),
121 static void enable_rgb(struct display_info_t
const *dev
)
123 SETUP_IOMUX_PADS(rgb_pads
);
126 struct display_info_t
const displays
[] = {
130 .pixfmt
= IPU_PIX_FMT_RGB666
,
132 .enable
= enable_rgb
,
146 .vmode
= FB_VMODE_NONINTERLACED
151 size_t display_count
= ARRAY_SIZE(displays
);
153 static void setup_display(void)
155 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
156 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
161 /* Turn on LDB0,IPU,IPU DI0 clocks */
162 reg
= __raw_readl(&mxc_ccm
->CCGR3
);
163 reg
|= (MXC_CCM_CCGR3_LDB_DI0_MASK
| 0xffff);
164 writel(reg
, &mxc_ccm
->CCGR3
);
166 /* set LDB0, LDB1 clk select to 011/011 */
167 reg
= readl(&mxc_ccm
->cs2cdr
);
168 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
169 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
);
170 reg
|= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
) |
171 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
);
172 writel(reg
, &mxc_ccm
->cs2cdr
);
174 reg
= readl(&mxc_ccm
->cscmr2
);
175 reg
|= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV
;
176 writel(reg
, &mxc_ccm
->cscmr2
);
178 reg
= readl(&mxc_ccm
->chsccdr
);
179 reg
|= (CHSCCDR_CLK_SEL_LDB_DI0
<<
180 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
);
181 writel(reg
, &mxc_ccm
->chsccdr
);
183 reg
= IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|
184 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
|
185 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|
186 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|
187 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|
188 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
189 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|
190 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
|
191 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
;
192 writel(reg
, &iomux
->gpr
[2]);
194 reg
= readl(&iomux
->gpr
[3]);
195 reg
= (reg
& ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
) |
196 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<
197 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET
);
198 writel(reg
, &iomux
->gpr
[3]);
200 #endif /* CONFIG_VIDEO_IPUV3 */
202 int board_early_init_f(void)
204 SETUP_IOMUX_PADS(uart4_pads
);
209 #ifdef CONFIG_ENV_IS_IN_MMC
210 static void mmc_late_init(void)
214 u32 dev_no
= mmc_get_env_dev();
216 setenv_ulong("mmcdev", dev_no
);
219 sprintf(mmcblk
, "/dev/mmcblk%dp2 rootwait rw", dev_no
);
220 setenv("mmcroot", mmcblk
);
222 sprintf(cmd
, "mmc dev %d", dev_no
);
227 int board_late_init(void)
229 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK
) >>
233 #ifdef CONFIG_ENV_IS_IN_MMC
236 setenv("modeboot", "mmcboot");
238 case IMX6_BMODE_NAND
:
239 setenv("modeboot", "nandboot");
242 setenv("modeboot", "");
247 setenv("fdt_file", "imx6q-icore.dtb");
248 else if(is_mx6dl() || is_mx6solo())
249 setenv("fdt_file", "imx6dl-icore.dtb");
256 /* Address of boot parameters */
257 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
259 #ifdef CONFIG_NAND_MXS
263 #ifdef CONFIG_VIDEO_IPUV3
272 gd
->ram_size
= imx_ddr_size();
277 #ifdef CONFIG_SPL_BUILD
281 #include <asm/arch/crm_regs.h>
282 #include <asm/arch/mx6-ddr.h>
284 /* MMC board initialization is needed till adding DM support in SPL */
285 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
287 #include <fsl_esdhc.h>
289 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
290 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
291 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
293 static iomux_v3_cfg_t
const usdhc1_pads
[] = {
294 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
295 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
296 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
297 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
298 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
299 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
300 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01
| MUX_PAD_CTRL(NO_PAD_CTRL
)),/* CD */
303 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
305 struct fsl_esdhc_cfg usdhc_cfg
[1] = {
306 {USDHC1_BASE_ADDR
, 0, 4},
309 int board_mmc_getcd(struct mmc
*mmc
)
311 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
314 switch (cfg
->esdhc_base
) {
315 case USDHC1_BASE_ADDR
:
316 ret
= !gpio_get_value(USDHC1_CD_GPIO
);
323 int board_mmc_init(bd_t
*bis
)
328 * According to the board_mmc_init() the following map is done:
329 * (U-boot device node) (Physical Port)
332 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
335 SETUP_IOMUX_PADS(usdhc1_pads
);
336 gpio_direction_input(USDHC1_CD_GPIO
);
337 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
340 printf("Warning - USDHC%d controller not supporting\n",
345 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
347 printf("Warning: failed to initialize mmc dev %d\n", i
);
356 #ifdef CONFIG_SPL_LOAD_FIT
357 int board_fit_config_name_match(const char *name
)
359 if (is_mx6dq() && !strcmp(name
, "imx6q-icore"))
361 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name
, "imx6dl-icore"))
374 #define IMX6DQ_DRIVE_STRENGTH 0x30
375 #define IMX6SDL_DRIVE_STRENGTH 0x28
377 /* configure MX6Q/DUAL mmdc DDR io registers */
378 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
397 .dram_sdclk_0
= 0x30,
398 .dram_sdclk_1
= 0x30,
400 .dram_sdcke0
= 0x3000,
401 .dram_sdcke1
= 0x3000,
402 .dram_sdba2
= 0x00000000,
407 /* configure MX6Q/DUAL mmdc GRP io registers */
408 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
418 .grp_ddrmode_ctl
= 0x00020000,
419 .grp_ddrpke
= 0x00000000,
420 .grp_ddrmode
= 0x00020000,
422 .grp_ddr_type
= 0x000c0000,
425 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
426 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
427 .dram_sdclk_0
= 0x30,
428 .dram_sdclk_1
= 0x30,
434 .dram_sdba2
= 0x00000000,
455 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
456 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
457 .grp_ddr_type
= 0x000c0000,
458 .grp_ddrmode_ctl
= 0x00020000,
459 .grp_ddrpke
= 0x00000000,
462 .grp_ddrmode
= 0x00020000,
474 static struct mx6_ddr3_cfg mt41j256
= {
488 static struct mx6_mmdc_calibration mx6dq_mmdc_calib
= {
489 .p0_mpwldectrl0
= 0x000E0009,
490 .p0_mpwldectrl1
= 0x0018000E,
491 .p1_mpwldectrl0
= 0x00000007,
492 .p1_mpwldectrl1
= 0x00000000,
493 .p0_mpdgctrl0
= 0x43280334,
494 .p0_mpdgctrl1
= 0x031C0314,
495 .p1_mpdgctrl0
= 0x4318031C,
496 .p1_mpdgctrl1
= 0x030C0258,
497 .p0_mprddlctl
= 0x3E343A40,
498 .p1_mprddlctl
= 0x383C3844,
499 .p0_mpwrdlctl
= 0x40404440,
500 .p1_mpwrdlctl
= 0x4C3E4446,
504 static struct mx6_ddr_sysinfo mem_q
= {
505 .ddr_type
= DDR_TYPE_DDR3
,
508 /* config for full 4GB range so that get_mem_size() works */
521 static struct mx6_mmdc_calibration mx6dl_mmdc_calib
= {
522 .p0_mpwldectrl0
= 0x001F0024,
523 .p0_mpwldectrl1
= 0x00110018,
524 .p1_mpwldectrl0
= 0x001F0024,
525 .p1_mpwldectrl1
= 0x00110018,
526 .p0_mpdgctrl0
= 0x4230022C,
527 .p0_mpdgctrl1
= 0x02180220,
528 .p1_mpdgctrl0
= 0x42440248,
529 .p1_mpdgctrl1
= 0x02300238,
530 .p0_mprddlctl
= 0x44444A48,
531 .p1_mprddlctl
= 0x46484A42,
532 .p0_mpwrdlctl
= 0x38383234,
533 .p1_mpwrdlctl
= 0x3C34362E,
537 static struct mx6_ddr_sysinfo mem_dl
= {
540 /* config for full 4GB range so that get_mem_size() works */
553 /* DDR 32bit 512MB */
554 static struct mx6_ddr_sysinfo mem_s
= {
557 /* config for full 4GB range so that get_mem_size() works */
570 static void ccgr_init(void)
572 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
574 writel(0x00003F3F, &ccm
->CCGR0
);
575 writel(0x0030FC00, &ccm
->CCGR1
);
576 writel(0x000FC000, &ccm
->CCGR2
);
577 writel(0x3F300000, &ccm
->CCGR3
);
578 writel(0xFF00F300, &ccm
->CCGR4
);
579 writel(0x0F0000C3, &ccm
->CCGR5
);
580 writel(0x000003CC, &ccm
->CCGR6
);
583 static void gpr_init(void)
585 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
587 /* enable AXI cache for VDOA/VPU/IPU */
588 writel(0xF00000CF, &iomux
->gpr
[4]);
589 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
590 writel(0x007F007F, &iomux
->gpr
[6]);
591 writel(0x007F007F, &iomux
->gpr
[7]);
594 static void spl_dram_init(void)
597 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
598 mx6_dram_cfg(&mem_s
, &mx6dl_mmdc_calib
, &mt41j256
);
599 } else if (is_mx6dl()) {
600 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
601 mx6_dram_cfg(&mem_dl
, &mx6dl_mmdc_calib
, &mt41j256
);
602 } else if (is_mx6dq()) {
603 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs
, &mx6dq_grp_ioregs
);
604 mx6_dram_cfg(&mem_q
, &mx6dq_mmdc_calib
, &mt41j256
);
610 void board_init_f(ulong dummy
)
614 /* setup AIPS and disable watchdog */
620 board_early_init_f();
625 /* UART clocks enabled and gd valid - init serial console */
626 preloader_console_init();
628 /* DDR initialization */
632 memset(__bss_start
, 0, __bss_end
- __bss_start
);
634 /* load/boot image from boot device */
635 board_init_r(NULL
, 0);