2 * (C) Copyright 2005-2008
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * (C) Copyright 2001-2003
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/processor.h>
17 #include <mtd/cfi_flash.h>
18 #include <asm/4xx_pci.h>
21 DECLARE_GLOBAL_DATA_PTR
;
25 extern void lxt971_no_sleep(void);
27 /* fpga configuration data - gzip compressed and generated by bin2c */
28 const unsigned char fpgadata
[] =
34 * include common fpga code (for esd boards)
36 #include "../common/fpga.c"
38 #ifdef CONFIG_LCD_USED
39 /* logo bitmap data - gzip compressed and generated by bin2c */
40 unsigned char logo_bmp
[] =
42 #include "logo_640_480_24bpp.c"
46 * include common lcd code (for esd boards)
48 #include "../common/lcd.c"
49 #include "../common/s1d13505_640_480_16bpp.h"
50 #include "../common/s1d13806_640_480_16bpp.h"
51 #endif /* CONFIG_LCD_USED */
54 * include common auto-update code (for esd boards)
56 #include "../common/auto_update.h"
58 au_image_t au_image
[] = {
59 {"preinst.img", 0, -1, AU_SCRIPT
},
60 {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE
| AU_PROTECT
},
61 {"pImage", 0xfe000000, 0x00100000, AU_NOR
| AU_PROTECT
},
62 {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR
| AU_PROTECT
},
63 {"work.img", 0xfe500000, 0x01400000, AU_NOR
},
64 {"data.img", 0xff900000, 0x00580000, AU_NOR
},
65 {"logo.img", 0xffe80000, 0x00100000, AU_NOR
| AU_PROTECT
},
66 {"postinst.img", 0, 0, AU_SCRIPT
},
69 int N_AU_IMAGES
= (sizeof(au_image
) / sizeof(au_image
[0]));
71 int board_revision(void)
73 unsigned long CPC0_CR0Reg
;
77 * Get version of APC405 board from GPIO's
80 /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
81 CPC0_CR0Reg
= mfdcr(CPC0_CR0
);
82 mtdcr(CPC0_CR0
, CPC0_CR0Reg
| 0x03800000);
83 out_be32((void*)GPIO0_ODR
, in_be32((void*)GPIO0_ODR
) & ~0x001c0000);
84 out_be32((void*)GPIO0_TCR
, in_be32((void*)GPIO0_TCR
) & ~0x001c0000);
86 /* wait some time before reading input */
90 value
= in_be32((void*)GPIO0_IR
) & 0x001c0000;
92 * Restore GPIO settings
94 mtdcr(CPC0_CR0
, CPC0_CR0Reg
);
98 /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
101 /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
104 /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
107 /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
110 /* should not be reached! */
115 int board_early_init_f (void)
118 * First pull fpga-prg pin low, to disable fpga logic
120 out_be32((void*)GPIO0_ODR
, 0x00000000); /* no open drain pins */
121 out_be32((void*)GPIO0_TCR
, CONFIG_SYS_FPGA_PRG
); /* setup for output */
122 out_be32((void*)GPIO0_OR
, 0); /* pull prg low */
125 * IRQ 0-15 405GP internally generated; active high; level sensitive
126 * IRQ 16 405GP internally generated; active low; level sensitive
128 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
129 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
130 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
131 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
132 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
133 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
134 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
136 mtdcr(UIC0SR
, 0xFFFFFFFF); /* clear all ints */
137 mtdcr(UIC0ER
, 0x00000000); /* disable all ints */
138 mtdcr(UIC0CR
, 0x00000000); /* set all to be non-critical*/
139 mtdcr(UIC0PR
, 0xFFFFFF81); /* set int polarities */
140 mtdcr(UIC0TR
, 0x10000000); /* set int trigger levels */
141 mtdcr(UIC0VCR
, 0x00000001); /* set vect base=0 */
142 mtdcr(UIC0SR
, 0xFFFFFFFF); /* clear all ints */
145 * EBC Configuration Register: set ready timeout to 512 ebc-clks
147 mtebc(EBC0_CFG
, 0xa8400000); /* ebc always driven */
150 * New boards have a single 32MB flash connected to CS0
151 * instead of two 16MB flashes on CS0+1.
153 if (board_revision() >= 8) {
158 /* resize CS0 to 32MB */
159 mtebc(PB0AP
, CONFIG_SYS_EBC_PB0AP_HWREV8
);
160 mtebc(PB0CR
, CONFIG_SYS_EBC_PB0CR_HWREV8
);
166 int board_early_init_r(void)
168 if (gd
->board_type
>= 8)
169 cfi_flash_num_flash_banks
= 1;
174 #define FUJI_BASE 0xf0100200
175 #define LCDBL_PWM 0xa0
176 #define LCDBL_PWMMIN 0xa4
177 #define LCDBL_PWMMAX 0xa8
179 int misc_init_r(void)
181 u16
*fpga_mode
= (u16
*)(CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
);
182 u16
*fpga_ctrl2
=(u16
*)(CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL2
);
183 u8
*duart0_mcr
= (u8
*)(DUART0_BA
+ 4);
184 u8
*duart1_mcr
= (u8
*)(DUART1_BA
+ 4);
186 ulong len
= sizeof(fpgadata
);
190 unsigned long CPC0_CR0Reg
;
198 * Setup GPIO pins (CS6+CS7 as GPIO)
200 CPC0_CR0Reg
= mfdcr(CPC0_CR0
);
201 mtdcr(CPC0_CR0
, CPC0_CR0Reg
| 0x00300000);
203 dst
= malloc(CONFIG_SYS_FPGA_MAX_SIZE
);
204 if (gunzip(dst
, CONFIG_SYS_FPGA_MAX_SIZE
, (uchar
*)fpgadata
, &len
) != 0) {
205 printf("GUNZIP ERROR - must RESET board to recover\n");
206 do_reset(NULL
, 0, 0, NULL
);
209 status
= fpga_boot(dst
, len
);
211 printf("\nFPGA: Booting failed ");
213 case ERROR_FPGA_PRG_INIT_LOW
:
215 "INIT not low after asserting PROGRAM*)\n ");
217 case ERROR_FPGA_PRG_INIT_HIGH
:
219 "INIT not high after deasserting PROGRAM*)\n ");
221 case ERROR_FPGA_PRG_DONE
:
223 "DONE not high after programming FPGA)\n ");
227 /* display infos on fpgaimage */
229 for (i
= 0; i
< 4; i
++) {
231 printf("FPGA: %s\n", &(dst
[index
+1]));
236 for (i
= 20; i
> 0; i
--) {
237 printf("Rebooting in %2d seconds \r",i
);
238 for (index
= 0; index
< 1000; index
++)
242 do_reset(NULL
, 0, 0, NULL
);
245 /* restore gpio/cs settings */
246 mtdcr(CPC0_CR0
, CPC0_CR0Reg
);
250 /* display infos on fpgaimage */
252 for (i
= 0; i
< 4; i
++) {
254 printf("%s ", &(dst
[index
+ 1]));
262 * Reset FPGA via FPGA_DATA pin
264 SET_FPGA(FPGA_PRG
| FPGA_CLK
);
265 udelay(1000); /* wait 1ms */
266 SET_FPGA(FPGA_PRG
| FPGA_CLK
| FPGA_DATA
);
267 udelay(1000); /* wait 1ms */
270 * Write board revision in FPGA
273 (in_be16(fpga_ctrl2
) & 0xfff0) | (gd
->board_type
& 0x000f));
276 * Enable power on PS/2 interface (with reset)
278 out_be16(fpga_mode
, in_be16(fpga_mode
) | CONFIG_SYS_FPGA_CTRL_PS2_RESET
);
282 out_be16(fpga_mode
, in_be16(fpga_mode
) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET
);
285 * Enable interrupts in exar duart mcr[3]
287 out_8(duart0_mcr
, 0x08);
288 out_8(duart1_mcr
, 0x08);
291 * Init lcd interface and display logo
293 str
= getenv("splashimage");
295 logo_addr
= (uchar
*)simple_strtoul(str
, NULL
, 16);
296 logo_size
= CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
;
298 logo_addr
= logo_bmp
;
299 logo_size
= sizeof(logo_bmp
);
302 if (gd
->board_type
>= 6) {
303 result
= lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
,
304 (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
305 regs_13505_640_480_16bpp
,
306 sizeof(regs_13505_640_480_16bpp
) /
307 sizeof(regs_13505_640_480_16bpp
[0]),
308 logo_addr
, logo_size
);
310 /* retry with internal image */
311 logo_addr
= logo_bmp
;
312 logo_size
= sizeof(logo_bmp
);
313 lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
,
314 (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
315 regs_13505_640_480_16bpp
,
316 sizeof(regs_13505_640_480_16bpp
) /
317 sizeof(regs_13505_640_480_16bpp
[0]),
318 logo_addr
, logo_size
);
321 result
= lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
,
322 (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
323 regs_13806_640_480_16bpp
,
324 sizeof(regs_13806_640_480_16bpp
) /
325 sizeof(regs_13806_640_480_16bpp
[0]),
326 logo_addr
, logo_size
);
328 /* retry with internal image */
329 logo_addr
= logo_bmp
;
330 logo_size
= sizeof(logo_bmp
);
331 lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
,
332 (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
333 regs_13806_640_480_16bpp
,
334 sizeof(regs_13806_640_480_16bpp
) /
335 sizeof(regs_13806_640_480_16bpp
[0]),
336 logo_addr
, logo_size
);
341 * Reset microcontroller and setup backlight PWM controller
343 out_be16(fpga_mode
, in_be16(fpga_mode
) | 0x0014);
346 out_be16(fpga_mode
, in_be16(fpga_mode
) | 0x001c);
350 str
= getenv("lcdbl");
352 minb
= (ushort
)simple_strtoul(str
, &str
, 16) & 0x00ff;
353 if (str
&& (*str
=',')) {
355 maxb
= (ushort
)simple_strtoul(str
, NULL
, 16) & 0x00ff;
359 out_be16((u16
*)(FUJI_BASE
+ LCDBL_PWMMIN
), minb
);
360 out_be16((u16
*)(FUJI_BASE
+ LCDBL_PWMMAX
), maxb
);
362 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb
, maxb
);
364 out_be16((u16
*)(FUJI_BASE
+ LCDBL_PWM
), 0xff);
367 * fix environment for field updated units
369 if (getenv("altbootcmd") == NULL
) {
370 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND
);
371 setenv("usbargs", CONFIG_SYS_USB_ARGS
);
372 setenv("bootcmd", CONFIG_BOOTCOMMAND
);
373 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND
);
374 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT
);
375 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND
);
383 * Check Board Identity:
385 int checkboard (void)
388 int i
= getenv_f("serial#", str
, sizeof(str
));
393 puts ("### No HW ID - assuming APC405");
398 gd
->board_type
= board_revision();
399 printf(", Rev. 1.%ld\n", gd
->board_type
);
404 #ifdef CONFIG_IDE_RESET
405 void ide_set_reset(int on
)
407 u16
*fpga_mode
= (u16
*)(CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
);
410 * Assert or deassert CompactFlash Reset Pin
414 in_be16(fpga_mode
) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET
);
417 in_be16(fpga_mode
) | CONFIG_SYS_FPGA_CTRL_CF_RESET
);
420 #endif /* CONFIG_IDE_RESET */
425 * Disable sleep mode in LXT971
430 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
431 int usb_board_init(void)
436 int usb_board_stop(void)
443 * This is required to make some very old Linux OHCI driver
444 * work after U-Boot has used the OHCI controller.
446 pci_read_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, &tmp
);
447 pci_write_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, (tmp
| 0x1000));
449 for (i
= 0; i
< 100; i
++)
452 pci_write_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, tmp
);
456 int usb_board_init_fail(void)
461 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */