board/esd/canbt/canbt.c

   1 /*
   2  * (C) Copyright 2001
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include "canbt.h"
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <command.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 /* ------------------------------------------------------------------------- */
  17
  18 #if 0
  19 #define FPGA_DEBUG
  20 #endif
  21
  22 /* fpga configuration data */
  23 const unsigned char fpgadata[] = {
  24 #include "fpgadata.c"
  25 };
  26
  27 /*
  28  * include common fpga code (for esd boards)
  29  */
  30 #include "../common/fpga.c"
  31
  32
  33 int board_early_init_f (void)
  34 {
  35         unsigned long CPC0_CR0Reg;
  36         int index, len, i;
  37         int status;
  38
  39         /*
  40          * Setup GPIO pins
  41          */
  42         CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff;
  43         CPC0_CR0Reg |= 0x0070f000;
  44         mtdcr (CPC0_CR0, CPC0_CR0Reg);
  45
  46 #ifdef FPGA_DEBUG
  47         /* set up serial port with default baudrate */
  48         (void) get_clocks ();
  49         gd->baudrate = CONFIG_BAUDRATE;
  50         serial_init ();
  51         console_init_f ();
  52 #endif
  53
  54         /*
  55          * Boot onboard FPGA
  56          */
  57         status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
  58         if (status != 0) {
  59                 /* booting FPGA failed */
  60 #ifndef FPGA_DEBUG
  61                 /* set up serial port with default baudrate */
  62                 (void) get_clocks ();
  63                 gd->baudrate = CONFIG_BAUDRATE;
  64                 serial_init ();
  65                 console_init_f ();
  66 #endif
  67                 printf ("\nFPGA: Booting failed ");
  68                 switch (status) {
  69                 case ERROR_FPGA_PRG_INIT_LOW:
  70                         printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
  71                         break;
  72                 case ERROR_FPGA_PRG_INIT_HIGH:
  73                         printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
  74                         break;
  75                 case ERROR_FPGA_PRG_DONE:
  76                         printf ("(Timeout: DONE not high after programming FPGA)\n ");
  77                         break;
  78                 }
  79
  80                 /* display infos on fpgaimage */
  81                 index = 15;
  82                 for (i = 0; i < 4; i++) {
  83                         len = fpgadata[index];
  84                         printf ("FPGA: %s\n", &(fpgadata[index + 1]));
  85                         index += len + 3;
  86                 }
  87                 putc ('\n');
  88                 /* delayed reboot */
  89                 for (i = 20; i > 0; i--) {
  90                         printf ("Rebooting in %2d seconds \r", i);
  91                         for (index = 0; index < 1000; index++)
  92                                 udelay (1000);
  93                 }
  94                 putc ('\n');
  95                 do_reset (NULL, 0, 0, NULL);
  96         }
  97
  98         /*
  99          * Setup port pins for normal operation
 100          */
 101         out_be32 ((void *)GPIO0_ODR, 0x00000000);       /* no open drain pins */
 102         out_be32 ((void *)GPIO0_TCR, 0x07038100);       /* setup for output */
 103         out_be32 ((void *)GPIO0_OR, 0x07030100);        /* set output pins to high (default) */
 104
 105         /*
 106          * IRQ 0-15  405GP internally generated; active high; level sensitive
 107          * IRQ 16    405GP internally generated; active low; level sensitive
 108          * IRQ 17-24 RESERVED
 109          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 110          * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
 111          * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
 112          * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
 113          * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
 114          * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 115          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 116          */
 117         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 118         mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
 119         mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
 120         mtdcr (UIC0PR, 0xFFFFFF81);     /* set int polarities */
 121         mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
 122         mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
 123         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 124
 125         return 0;
 126 }
 127
 128
 129 /* ------------------------------------------------------------------------- */
 130
 131 /*
 132  * Check Board Identity:
 133  */
 134
 135 int checkboard (void)
 136 {
 137         int index;
 138         int len;
 139         char str[64];
 140         int i = getenv_f("serial#", str, sizeof (str));
 141
 142         puts ("Board: ");
 143
 144         if (!i || strncmp (str, "CANBT", 5)) {
 145                 puts ("### No HW ID - assuming CANBT\n");
 146                 return (0);
 147         }
 148
 149         puts (str);
 150
 151         puts ("\nFPGA:  ");
 152
 153         /* display infos on fpgaimage */
 154         index = 15;
 155         for (i = 0; i < 4; i++) {
 156                 len = fpgadata[index];
 157                 printf ("%s ", &(fpgadata[index + 1]));
 158                 index += len + 3;
 159         }
 160
 161         putc ('\n');
 162
 163         return 0;
 164 }