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git.ipfire.org Git - people/ms/u-boot.git/blob - board/esd/cms700/cms700.c
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 extern void lxt971_no_sleep(void);
33 /* fpga configuration data - not compressed, generated by bin2c */
34 const unsigned char fpgadata
[] =
38 int filesize
= sizeof(fpgadata
);
41 int board_early_init_f (void)
44 * IRQ 0-15 405GP internally generated; active high; level sensitive
45 * IRQ 16 405GP internally generated; active low; level sensitive
47 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
48 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
49 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
50 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
51 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
52 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
53 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
55 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
56 mtdcr(uicer
, 0x00000000); /* disable all ints */
57 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
58 mtdcr(uicpr
, 0xFFFFFF80); /* set int polarities */
59 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
60 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority*/
61 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
64 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
66 mtebc (epcr
, 0xa8400000); /* ebc always driven */
69 * Reset CPLD via GPIO12 (CS3) pin
71 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~CFG_PLD_RESET
);
72 udelay(1000); /* wait 1ms */
73 out32(GPIO0_OR
, in32(GPIO0_OR
) | CFG_PLD_RESET
);
74 udelay(1000); /* wait 1ms */
80 /* ------------------------------------------------------------------------- */
82 int misc_init_f (void)
84 return 0; /* dummy implementation */
88 int misc_init_r (void)
90 DECLARE_GLOBAL_DATA_PTR
;
92 /* adjust flash start and offset */
93 gd
->bd
->bi_flashstart
= 0 - gd
->bd
->bi_flashsize
;
94 gd
->bd
->bi_flashoffset
= 0;
97 * Setup and enable EEPROM write protection
99 out32(GPIO0_OR
, in32(GPIO0_OR
) | CFG_EEPROM_WP
);
102 * Set NAND-FLASH GPIO signals to default
104 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~(CFG_NAND_CLE
| CFG_NAND_ALE
));
105 out32(GPIO0_OR
, in32(GPIO0_OR
) | CFG_NAND_CE
);
112 * Check Board Identity:
115 int checkboard (void)
117 unsigned char str
[64];
120 volatile unsigned char *led_reg
= (unsigned char *)((ulong
)CFG_PLD_BASE
+ 0x1000);
121 volatile unsigned char *ver_reg
= (unsigned char *)((ulong
)CFG_PLD_BASE
+ 0x1001);
125 if (getenv_r("serial#", str
, sizeof(str
)) == -1) {
126 puts ("### No HW ID - assuming CMS700");
131 printf(" (PLD-Version=%02d)\n", *ver_reg
);
136 for (flashcnt
= 0; flashcnt
< 3; flashcnt
++) {
137 *led_reg
= 0x00; /* LEDs off */
138 for (delay
= 0; delay
< 100; delay
++)
140 *led_reg
= 0x0f; /* LEDs on */
141 for (delay
= 0; delay
< 50; delay
++)
149 /* ------------------------------------------------------------------------- */
151 long int initdram (int board_type
)
155 mtdcr(memcfga
, mem_mb0cf
);
156 val
= mfdcr(memcfgd
);
159 printf("\nmb0cf=%x\n", val
); /* test-only */
160 printf("strap=%x\n", mfdcr(strap
)); /* test-only */
163 return (4*1024*1024 << ((val
& 0x000e0000) >> 17));
166 /* ------------------------------------------------------------------------- */
168 #if defined(CFG_EEPROM_WREN)
169 /* Input: <dev_addr> I2C address of EEPROM device to enable.
170 * <state> -1: deliver current state
173 * Returns: -1: wrong device address
174 * 0: dis-/en- able done
175 * 0/1: current state if <state> was -1.
177 int eeprom_write_enable (unsigned dev_addr
, int state
)
179 if (CFG_I2C_EEPROM_ADDR
!= dev_addr
) {
184 /* Enable write access, clear bit GPIO_SINT2. */
185 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~CFG_EEPROM_WP
);
189 /* Disable write access, set bit GPIO_SINT2. */
190 out32(GPIO0_OR
, in32(GPIO0_OR
) | CFG_EEPROM_WP
);
194 /* Read current status back. */
195 state
= (0 == (in32(GPIO0_OR
) & CFG_EEPROM_WP
));
202 int do_eep_wren (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
204 int query
= argc
== 1;
208 /* Query write access state. */
209 state
= eeprom_write_enable (CFG_I2C_EEPROM_ADDR
, -1);
211 puts ("Query of write access state failed.\n");
213 printf ("Write access for device 0x%0x is %sabled.\n",
214 CFG_I2C_EEPROM_ADDR
, state
? "en" : "dis");
218 if ('0' == argv
[1][0]) {
219 /* Disable write access. */
220 state
= eeprom_write_enable (CFG_I2C_EEPROM_ADDR
, 0);
222 /* Enable write access. */
223 state
= eeprom_write_enable (CFG_I2C_EEPROM_ADDR
, 1);
226 puts ("Setup of write access state failed.\n");
233 U_BOOT_CMD(eepwren
, 2, 0, do_eep_wren
,
234 "eepwren - Enable / disable / query EEPROM write access\n",
236 #endif /* #if defined(CFG_EEPROM_WREN) */
238 /* ------------------------------------------------------------------------- */
240 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
241 #include <linux/mtd/nand.h>
242 extern struct nand_chip nand_dev_desc
[CFG_MAX_NAND_DEVICE
];
246 nand_probe(CFG_NAND_BASE
);
247 if (nand_dev_desc
[0].ChipID
!= NAND_ChipID_UNKNOWN
) {
248 print_size(nand_dev_desc
[0].totlen
, "\n");
255 #ifdef CONFIG_LXT971_NO_SLEEP
258 * Disable sleep mode in LXT971