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git.ipfire.org Git - people/ms/u-boot.git/blob - board/esd/cms700/cms700.c
2 * (C) Copyright 2005-2007
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR
;
32 extern void lxt971_no_sleep(void);
34 /* fpga configuration data - not compressed, generated by bin2c */
35 const unsigned char fpgadata
[] =
39 int filesize
= sizeof(fpgadata
);
42 int board_early_init_f (void)
45 * IRQ 0-15 405GP internally generated; active high; level sensitive
46 * IRQ 16 405GP internally generated; active low; level sensitive
48 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
49 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
50 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
51 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
52 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
53 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
54 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
56 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
57 mtdcr(uicer
, 0x00000000); /* disable all ints */
58 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
59 mtdcr(uicpr
, 0xFFFFFF80); /* set int polarities */
60 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
61 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority*/
62 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
65 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
67 mtebc (epcr
, 0xa8400000); /* ebc always driven */
70 * Reset CPLD via GPIO12 (CS3) pin
72 out_be32((void *)GPIO0_OR
, in_be32((void *)GPIO0_OR
) & ~CFG_PLD_RESET
);
73 udelay(1000); /* wait 1ms */
74 out_be32((void *)GPIO0_OR
, in_be32((void *)GPIO0_OR
) | CFG_PLD_RESET
);
75 udelay(1000); /* wait 1ms */
81 /* ------------------------------------------------------------------------- */
83 int misc_init_f (void)
85 return 0; /* dummy implementation */
89 int misc_init_r (void)
91 /* adjust flash start and offset */
92 gd
->bd
->bi_flashstart
= 0 - gd
->bd
->bi_flashsize
;
93 gd
->bd
->bi_flashoffset
= 0;
96 * Setup and enable EEPROM write protection
98 out_be32((void *)GPIO0_OR
, in_be32((void *)GPIO0_OR
) | CFG_EEPROM_WP
);
105 * Check Board Identity:
108 int checkboard (void)
113 volatile unsigned char *led_reg
= (unsigned char *)((ulong
)CFG_PLD_BASE
+ 0x1000);
114 volatile unsigned char *ver_reg
= (unsigned char *)((ulong
)CFG_PLD_BASE
+ 0x1001);
118 if (getenv_r("serial#", str
, sizeof(str
)) == -1) {
119 puts ("### No HW ID - assuming CMS700");
124 printf(" (PLD-Version=%02d)\n", *ver_reg
);
129 for (flashcnt
= 0; flashcnt
< 3; flashcnt
++) {
130 *led_reg
= 0x00; /* LEDs off */
131 for (delay
= 0; delay
< 100; delay
++)
133 *led_reg
= 0x0f; /* LEDs on */
134 for (delay
= 0; delay
< 50; delay
++)
142 /* ------------------------------------------------------------------------- */
144 phys_size_t
initdram (int board_type
)
148 mtdcr(memcfga
, mem_mb0cf
);
149 val
= mfdcr(memcfgd
);
151 return (4*1024*1024 << ((val
& 0x000e0000) >> 17));
154 /* ------------------------------------------------------------------------- */
156 #if defined(CFG_EEPROM_WREN)
157 /* Input: <dev_addr> I2C address of EEPROM device to enable.
158 * <state> -1: deliver current state
161 * Returns: -1: wrong device address
162 * 0: dis-/en- able done
163 * 0/1: current state if <state> was -1.
165 int eeprom_write_enable (unsigned dev_addr
, int state
)
167 if (CFG_I2C_EEPROM_ADDR
!= dev_addr
) {
172 /* Enable write access, clear bit GPIO_SINT2. */
173 out_be32((void *)GPIO0_OR
, in_be32((void *)GPIO0_OR
) & ~CFG_EEPROM_WP
);
177 /* Disable write access, set bit GPIO_SINT2. */
178 out_be32((void *)GPIO0_OR
, in_be32((void *)GPIO0_OR
) | CFG_EEPROM_WP
);
182 /* Read current status back. */
183 state
= (0 == (in_be32((void *)GPIO0_OR
) & CFG_EEPROM_WP
));
190 int do_eep_wren (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
192 int query
= argc
== 1;
196 /* Query write access state. */
197 state
= eeprom_write_enable (CFG_I2C_EEPROM_ADDR
, -1);
199 puts ("Query of write access state failed.\n");
201 printf ("Write access for device 0x%0x is %sabled.\n",
202 CFG_I2C_EEPROM_ADDR
, state
? "en" : "dis");
206 if ('0' == argv
[1][0]) {
207 /* Disable write access. */
208 state
= eeprom_write_enable (CFG_I2C_EEPROM_ADDR
, 0);
210 /* Enable write access. */
211 state
= eeprom_write_enable (CFG_I2C_EEPROM_ADDR
, 1);
214 puts ("Setup of write access state failed.\n");
221 U_BOOT_CMD(eepwren
, 2, 0, do_eep_wren
,
222 "eepwren - Enable / disable / query EEPROM write access\n",
224 #endif /* #if defined(CFG_EEPROM_WREN) */
226 /* ------------------------------------------------------------------------- */
230 #ifdef CONFIG_LXT971_NO_SLEEP
233 * Disable sleep mode in LXT971