board/esd/cpci2dp/cpci2dp.c

   1 /*
   2  * (C) Copyright 2005
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <command.h>
  27 #include <malloc.h>
  28
  29 int board_early_init_f (void)
  30 {
  31         unsigned long cntrl0Reg;
  32
  33         /*
  34          * Setup GPIO pins (CS4 as GPIO)
  35          */
  36         cntrl0Reg = mfdcr(cntrl0);
  37         mtdcr(cntrl0, cntrl0Reg | 0x00800000);
  38
  39         out32(GPIO0_OR,  CFG_INTA_FAKE | CFG_EEPROM_WP); /* set output pins to high */
  40         out32(GPIO0_ODR, CFG_INTA_FAKE);                 /* INTA# is open drain */
  41         out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* setup for output        */
  42
  43         /*
  44          * IRQ 0-15  405GP internally generated; active high; level sensitive
  45          * IRQ 16    405GP internally generated; active low; level sensitive
  46          * IRQ 17-24 RESERVED
  47          * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
  48          * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
  49          * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
  50          * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
  51          * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  52          * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
  53          * IRQ 31 (EXT IRQ 6) unused
  54          */
  55         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  56         mtdcr(uicer, 0x00000000);       /* disable all ints */
  57         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
  58         mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
  59
  60         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
  61         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  62         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  63
  64         return 0;
  65 }
  66
  67
  68 int misc_init_f (void)
  69 {
  70         return 0;  /* dummy implementation */
  71 }
  72
  73
  74 int misc_init_r (void)
  75 {
  76         DECLARE_GLOBAL_DATA_PTR;
  77         unsigned long cntrl0Reg;
  78
  79         /* adjust flash start and offset */
  80         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  81         gd->bd->bi_flashoffset = 0;
  82
  83         /*
  84          * Select cts (and not dsr) on uart1
  85          */
  86         cntrl0Reg = mfdcr(cntrl0);
  87         mtdcr(cntrl0, cntrl0Reg | 0x00001000);
  88
  89         return (0);
  90 }
  91
  92
  93 /*
  94  * Check Board Identity:
  95  */
  96 int checkboard (void)
  97 {
  98         char str[64];
  99         int i = getenv_r ("serial#", str, sizeof(str));
 100
 101         puts ("Board: ");
 102
 103         if (i == -1) {
 104                 puts ("### No HW ID - assuming CPCI2DP");
 105         } else {
 106                 puts(str);
 107         }
 108
 109         printf(" (Ver 1.0)");
 110
 111         putc ('\n');
 112
 113         return 0;
 114 }
 115
 116 /* ------------------------------------------------------------------------- */
 117
 118 long int initdram (int board_type)
 119 {
 120         unsigned long val;
 121
 122         mtdcr(memcfga, mem_mb0cf);
 123         val = mfdcr(memcfgd);
 124
 125         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 126 }
 127
 128 /* ------------------------------------------------------------------------- */
 129
 130 int testdram (void)
 131 {
 132         /* TODO: XXX XXX XXX */
 133         printf ("test: 64 MB - ok\n");
 134
 135         return (0);
 136 }
 137
 138 /* ------------------------------------------------------------------------- */
 139
 140 #if defined(CFG_EEPROM_WREN)
 141 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 142  *         <state>     -1: deliver current state
 143  *                     0: disable write
 144  *                     1: enable write
 145  *  Returns:           -1: wrong device address
 146  *                      0: dis-/en- able done
 147  *                   0/1: current state if <state> was -1.
 148  */
 149 int eeprom_write_enable (unsigned dev_addr, int state) {
 150         if (CFG_I2C_EEPROM_ADDR != dev_addr) {
 151                 return -1;
 152         }
 153         else {
 154                 switch (state) {
 155                 case 1:
 156                         /* Enable write access, clear bit GPIO_SINT2. */
 157                         out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
 158                         state = 0;
 159                         break;
 160                 case 0:
 161                         /* Disable write access, set bit GPIO_SINT2. */
 162                         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
 163                         state = 0;
 164                         break;
 165                 default:
 166                         /* Read current status back. */
 167                         state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
 168                         break;
 169                 }
 170         }
 171         return state;
 172 }
 173 #endif
 174
 175 #if defined(CFG_EEPROM_WREN)
 176 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 177 {
 178         int query = argc == 1;
 179         int state = 0;
 180
 181         if (query) {
 182                 /* Query write access state. */
 183                 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
 184                 if (state < 0) {
 185                         puts ("Query of write access state failed.\n");
 186                 }
 187                 else {
 188                         printf ("Write access for device 0x%0x is %sabled.\n",
 189                                 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
 190                         state = 0;
 191                 }
 192         }
 193         else {
 194                 if ('0' == argv[1][0]) {
 195                         /* Disable write access. */
 196                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
 197                 }
 198                 else {
 199                         /* Enable write access. */
 200                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
 201                 }
 202                 if (state < 0) {
 203                         puts ("Setup of write access state failed.\n");
 204                 }
 205         }
 206
 207         return state;
 208 }
 209
 210 U_BOOT_CMD(
 211            eepwren,     2,      0,      do_eep_wren,
 212            "eepwren - Enable / disable / query EEPROM write access\n",
 213            NULL
 214            );
 215 #endif /* #if defined(CFG_EEPROM_WREN) */