2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
32 DECLARE_GLOBAL_DATA_PTR
;
34 extern int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[]); /*cmd_boot.c*/
39 /* fpga configuration data - generated by bin2cc */
40 const unsigned char fpgadata
[] =
42 #ifdef CONFIG_CPCI405_VER2
43 # ifdef CONFIG_CPCI405AB
44 # include "fpgadata_cpci405ab.c"
46 # include "fpgadata_cpci4052.c"
49 # include "fpgadata_cpci405.c"
54 * include common fpga code (for esd boards)
56 #include "../common/fpga.c"
57 #include "../common/auto_update.h"
59 #ifdef CONFIG_CPCI405AB
60 au_image_t au_image
[] = {
61 {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT
},
62 {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR
},
63 {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR
},
64 {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE
},
65 {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT
},
68 #ifdef CONFIG_CPCI405_VER2
69 au_image_t au_image
[] = {
70 {"cpci4052/preinst.img", 0, -1, AU_SCRIPT
},
71 {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR
},
72 {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR
},
73 {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE
},
74 {"cpci4052/postinst.img", 0, 0, AU_SCRIPT
},
77 au_image_t au_image
[] = {
78 {"cpci405/preinst.img", 0, -1, AU_SCRIPT
},
79 {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR
},
80 {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR
},
81 {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE
},
82 {"cpci405/postinst.img", 0, 0, AU_SCRIPT
},
87 int N_AU_IMAGES
= (sizeof(au_image
) / sizeof(au_image
[0]));
90 int cpci405_version(void);
91 int gunzip(void *, int, unsigned char *, unsigned long *);
92 void lxt971_no_sleep(void);
94 int board_early_init_f (void)
96 #ifndef CONFIG_CPCI405_VER2
102 /* set up serial port with default baudrate */
103 (void) get_clocks ();
104 gd
->baudrate
= CONFIG_BAUDRATE
;
110 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
112 out32(GPIO0_ODR
, 0x00000000); /* no open drain pins */
113 out32(GPIO0_TCR
, CFG_FPGA_PRG
); /* setup for output */
114 out32(GPIO0_OR
, CFG_FPGA_PRG
); /* set output pins to high */
115 out32(GPIO0_OR
, 0); /* pull prg low */
120 #ifndef CONFIG_CPCI405_VER2
121 if (cpci405_version() == 1) {
122 status
= fpga_boot((unsigned char *)fpgadata
, sizeof(fpgadata
));
124 /* booting FPGA failed */
126 /* set up serial port with default baudrate */
127 (void) get_clocks ();
128 gd
->baudrate
= CONFIG_BAUDRATE
;
132 printf("\nFPGA: Booting failed ");
134 case ERROR_FPGA_PRG_INIT_LOW
:
135 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
137 case ERROR_FPGA_PRG_INIT_HIGH
:
138 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
140 case ERROR_FPGA_PRG_DONE
:
141 printf("(Timeout: DONE not high after programming FPGA)\n ");
145 /* display infos on fpgaimage */
147 for (i
=0; i
<4; i
++) {
148 len
= fpgadata
[index
];
149 printf("FPGA: %s\n", &(fpgadata
[index
+1]));
154 for (i
=20; i
>0; i
--) {
155 printf("Rebooting in %2d seconds \r",i
);
156 for (index
=0;index
<1000;index
++)
160 do_reset(NULL
, 0, 0, NULL
);
163 #endif /* !CONFIG_CPCI405_VER2 */
166 * IRQ 0-15 405GP internally generated; active high; level sensitive
167 * IRQ 16 405GP internally generated; active low; level sensitive
169 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
170 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
171 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
172 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
173 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
174 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
175 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
177 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
178 mtdcr(uicer
, 0x00000000); /* disable all ints */
179 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
180 #ifdef CONFIG_CPCI405_6U
181 if (cpci405_version() == 3) {
182 mtdcr(uicpr
, 0xFFFFFF99); /* set int polarities */
184 mtdcr(uicpr
, 0xFFFFFF81); /* set int polarities */
187 mtdcr(uicpr
, 0xFFFFFF81); /* set int polarities */
189 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
190 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority*/
191 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
196 /* ------------------------------------------------------------------------- */
200 #ifdef CONFIG_CPCI405_VER2
201 return 0; /* no, board is cpci405 */
203 if ((*(unsigned char *)0xf0000400 == 0x00) &&
204 (*(unsigned char *)0xf0000401 == 0x01))
205 return 0; /* no, board is cpci405 */
207 return -1; /* yes, board is cterm-m2 */
211 int cpci405_host(void)
213 if (mfdcr(strap
) & PSR_PCI_ARBIT_EN
)
214 return -1; /* yes, board is cpci405 host */
216 return 0; /* no, board is cpci405 adapter */
219 int cpci405_version(void)
221 unsigned long cntrl0Reg
;
225 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
227 cntrl0Reg
= mfdcr(cntrl0
);
228 mtdcr(cntrl0
, cntrl0Reg
| 0x03000000);
229 out_be32((void*)GPIO0_ODR
, in_be32((void*)GPIO0_ODR
) & ~0x00180000);
230 out_be32((void*)GPIO0_TCR
, in_be32((void*)GPIO0_TCR
) & ~0x00180000);
231 udelay(1000); /* wait some time before reading input */
232 value
= in_be32((void*)GPIO0_IR
) & 0x00180000; /* get config bits */
235 * Restore GPIO settings
237 mtdcr(cntrl0
, cntrl0Reg
);
241 /* CS2==1 && CS3==1 -> version 1 */
244 /* CS2==0 && CS3==1 -> version 2 */
247 /* CS2==1 && CS3==0 -> version 3 or 6U board */
250 /* CS2==0 && CS3==0 -> version 4 */
253 /* should not be reached! */
258 int misc_init_r (void)
260 unsigned long cntrl0Reg
;
262 /* adjust flash start and offset */
263 gd
->bd
->bi_flashstart
= 0 - gd
->bd
->bi_flashsize
;
264 gd
->bd
->bi_flashoffset
= 0;
266 #ifdef CONFIG_CPCI405_VER2
269 ulong len
= sizeof(fpgadata
);
275 * On CPCI-405 version 2 the environment is saved in eeprom!
276 * FPGA can be gzip compressed (malloc) and booted this late.
278 if (cpci405_version() >= 2) {
280 * Setup GPIO pins (CS6+CS7 as GPIO)
282 cntrl0Reg
= mfdcr(cntrl0
);
283 mtdcr(cntrl0
, cntrl0Reg
| 0x00300000);
285 dst
= malloc(CFG_FPGA_MAX_SIZE
);
286 if (gunzip (dst
, CFG_FPGA_MAX_SIZE
, (uchar
*)fpgadata
, &len
) != 0) {
287 printf ("GUNZIP ERROR - must RESET board to recover\n");
288 do_reset (NULL
, 0, 0, NULL
);
291 status
= fpga_boot(dst
, len
);
293 printf("\nFPGA: Booting failed ");
295 case ERROR_FPGA_PRG_INIT_LOW
:
296 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
298 case ERROR_FPGA_PRG_INIT_HIGH
:
299 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
301 case ERROR_FPGA_PRG_DONE
:
302 printf("(Timeout: DONE not high after programming FPGA)\n ");
306 /* display infos on fpgaimage */
308 for (i
=0; i
<4; i
++) {
310 printf("FPGA: %s\n", &(dst
[index
+1]));
315 for (i
=20; i
>0; i
--) {
316 printf("Rebooting in %2d seconds \r",i
);
317 for (index
=0;index
<1000;index
++)
321 do_reset(NULL
, 0, 0, NULL
);
324 /* restore gpio/cs settings */
325 mtdcr(cntrl0
, cntrl0Reg
);
329 /* display infos on fpgaimage */
331 for (i
=0; i
<4; i
++) {
333 printf("%s ", &(dst
[index
+1]));
341 * Reset FPGA via FPGA_DATA pin
343 SET_FPGA(FPGA_PRG
| FPGA_CLK
);
344 udelay(1000); /* wait 1ms */
345 SET_FPGA(FPGA_PRG
| FPGA_CLK
| FPGA_DATA
);
346 udelay(1000); /* wait 1ms */
348 #ifdef CONFIG_CPCI405_6U
349 if (cpci405_version() == 3) {
350 volatile unsigned short *fpga_mode
= (unsigned short *)CFG_FPGA_BASE_ADDR
;
351 volatile unsigned char *leds
= (unsigned char *)CFG_LED_ADDR
;
354 * Enable outputs in fpga on version 3 board
356 *fpga_mode
|= CFG_FPGA_MODE_ENABLE_OUTPUT
;
364 * Reset external DUART
366 *fpga_mode
|= CFG_FPGA_MODE_DUART_RESET
;
368 *fpga_mode
&= ~(CFG_FPGA_MODE_DUART_RESET
);
373 puts("\n*** U-Boot Version does not match Board Version!\n");
374 puts("*** CPCI-405 Version 1.x detected!\n");
375 puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
379 #else /* CONFIG_CPCI405_VER2 */
381 #if 0 /* test-only: code-plug now not relavant for ip-address any more */
383 * Generate last byte of ip-addr from code-plug @ 0xf0000400
387 unsigned char ipbyte
= *(unsigned char *)0xf0000400;
390 * Only overwrite ip-addr with allowed values
392 if ((ipbyte
!= 0x00) && (ipbyte
!= 0xff)) {
393 bd
->bi_ip_addr
= (bd
->bi_ip_addr
& 0xffffff00) | ipbyte
;
394 sprintf(str
, "%ld.%ld.%ld.%ld",
395 (bd
->bi_ip_addr
& 0xff000000) >> 24,
396 (bd
->bi_ip_addr
& 0x00ff0000) >> 16,
397 (bd
->bi_ip_addr
& 0x0000ff00) >> 8,
398 (bd
->bi_ip_addr
& 0x000000ff));
399 setenv("ipaddr", str
);
404 if (cpci405_version() >= 2) {
405 puts("\n*** U-Boot Version does not match Board Version!\n");
406 puts("*** CPCI-405 Board Version 2.x detected!\n");
407 puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
410 #endif /* CONFIG_CPCI405_VER2 */
413 * Select cts (and not dsr) on uart1
415 cntrl0Reg
= mfdcr(cntrl0
);
416 mtdcr(cntrl0
, cntrl0Reg
| 0x00001000);
422 * Check Board Identity:
425 int checkboard (void)
427 #ifndef CONFIG_CPCI405_VER2
432 int i
= getenv_r ("serial#", str
, sizeof(str
));
438 puts ("### No HW ID - assuming CPCI405");
443 ver
= cpci405_version();
444 printf(" (Ver %d.x, ", ver
);
446 #if 0 /* test-only */
448 volatile u16
*fpga_status
= (u16
*)CFG_FPGA_BASE_ADDR
+ 1;
450 if (*fpga_status
& CFG_FPGA_STATUS_FLASH
) {
451 puts ("FLASH Bank B, ");
453 puts ("FLASH Bank A, ");
462 * Read board-id and save in env-variable
464 sprintf(str
, "%d", *(unsigned char *)0xf0000400);
465 setenv("boardid", str
);
466 printf("CTERM-M2 - Id=%s)", str
);
468 if (cpci405_host()) {
469 puts ("PCI Host Version)");
471 puts ("PCI Adapter Version)");
475 #ifndef CONFIG_CPCI405_VER2
478 /* display infos on fpgaimage */
480 for (i
=0; i
<4; i
++) {
481 len
= fpgadata
[index
];
482 printf("%s ", &(fpgadata
[index
+1]));
493 #ifdef CONFIG_LXT971_NO_SLEEP
496 * Disable sleep mode in LXT971
502 #ifdef CONFIG_CPCI405_VER2
503 #ifdef CONFIG_IDE_RESET
505 void ide_set_reset(int on
)
507 volatile unsigned short *fpga_mode
= (unsigned short *)CFG_FPGA_BASE_ADDR
;
510 * Assert or deassert CompactFlash Reset Pin
512 if (on
) { /* assert RESET */
513 *fpga_mode
&= ~(CFG_FPGA_MODE_CF_RESET
);
514 } else { /* release RESET */
515 *fpga_mode
|= CFG_FPGA_MODE_CF_RESET
;
519 #endif /* CONFIG_IDE_RESET */
520 #endif /* CONFIG_CPCI405_VER2 */
522 #if defined(CONFIG_PCI)
523 void cpci405_pci_fixup_irq(struct pci_controller
*hose
, pci_dev_t dev
)
525 unsigned char int_line
= 0xff;
528 * Write pci interrupt line register (cpci405 specific)
530 switch (PCI_DEV(dev
) & 0x03) {
545 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
, int_line
);
548 int pci_pre_init(struct pci_controller
*hose
)
550 hose
->fixup_irq
= cpci405_pci_fixup_irq
;
553 #endif /* defined(CONFIG_PCI) */
556 #ifdef CONFIG_CPCI405AB
558 #define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
559 |= CFG_FPGA_MODE_1WIRE_DIR)
560 #define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
561 &= ~CFG_FPGA_MODE_1WIRE_DIR)
562 #define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
563 & CFG_FPGA_MODE_1WIRE)
566 * Generate a 1-wire reset, return 1 if no presence detect was found,
567 * return 0 otherwise.
568 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
570 int OWTouchReset(void)
579 result
= ONE_WIRE_GET
;
586 * Send 1 a 1-wire write bit.
587 * Provide 10us recovery time.
589 void OWWriteBit(int bit
)
611 * Read a bit from the 1-wire bus and return it.
612 * Provide 10us recovery time.
623 result
= ONE_WIRE_GET
;
629 void OWWriteByte(int data
)
633 for (loop
=0; loop
<8; loop
++) {
634 OWWriteBit(data
& 0x01);
641 int loop
, result
= 0;
643 for (loop
=0; loop
<8; loop
++) {
653 int do_onewire(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
655 volatile unsigned short val
;
658 unsigned char ow_id
[6];
660 unsigned char ow_crc
;
663 * Clear 1-wire bit (open drain with pull-up)
665 val
= *(volatile unsigned short *)0xf0400000;
666 val
&= ~0x1000; /* clear 1-wire bit */
667 *(volatile unsigned short *)0xf0400000 = val
;
669 result
= OWTouchReset();
671 puts("No 1-wire device detected!\n");
674 OWWriteByte(0x33); /* send read rom command */
675 OWReadByte(); /* skip family code ( == 0x01) */
676 for (i
=0; i
<6; i
++) {
677 ow_id
[i
] = OWReadByte();
679 ow_crc
= OWReadByte(); /* read crc */
681 sprintf(str
, "%08X%04X", *(unsigned int *)&ow_id
[0], *(unsigned short *)&ow_id
[4]);
682 printf("Setting environment variable 'ow_id' to %s\n", str
);
683 setenv("ow_id", str
);
688 onewire
, 1, 1, do_onewire
,
689 "onewire - Read 1-write ID\n",
693 #define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
694 #define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
697 * Write backplane ip-address...
699 int do_get_bpip(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
708 buf
= malloc(CFG_ENV_SIZE_2
);
709 if (eeprom_read(CFG_I2C_EEPROM_ADDR_2
, 0, (uchar
*)buf
, CFG_ENV_SIZE_2
)) {
710 puts("\nError reading backplane EEPROM!\n");
712 crc
= crc32(0, (uchar
*)(buf
+4), CFG_ENV_SIZE_2
-4);
713 if (crc
!= *(ulong
*)buf
) {
714 printf("ERROR: crc mismatch %08lx %08lx\n", crc
, *(ulong
*)buf
);
721 ptr
= strstr(buf
+4, "bp_ip=");
723 printf("ERROR: bp_ip not found!\n");
727 ipaddr
= string_to_ip(ptr
);
730 * Update whole ip-addr
732 bd
->bi_ip_addr
= ipaddr
;
733 sprintf(str
, "%ld.%ld.%ld.%ld",
734 (bd
->bi_ip_addr
& 0xff000000) >> 24,
735 (bd
->bi_ip_addr
& 0x00ff0000) >> 16,
736 (bd
->bi_ip_addr
& 0x0000ff00) >> 8,
737 (bd
->bi_ip_addr
& 0x000000ff));
738 setenv("ipaddr", str
);
739 printf("Updated ip_addr from bp_eeprom to %s!\n", str
);
747 getbpip
, 1, 1, do_get_bpip
,
748 "getbpip - Update IP-Address with Backplane IP-Address\n",
753 * Set and print backplane ip...
755 int do_set_bpip(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
766 printf("Setting bp_ip to %s\n", argv
[1]);
767 buf
= malloc(CFG_ENV_SIZE_2
);
768 memset(buf
, 0, CFG_ENV_SIZE_2
);
769 sprintf(str
, "bp_ip=%s", argv
[1]);
771 crc
= crc32(0, (uchar
*)(buf
+4), CFG_ENV_SIZE_2
-4);
774 if (eeprom_write(CFG_I2C_EEPROM_ADDR_2
, 0, (uchar
*)buf
, CFG_ENV_SIZE_2
)) {
775 puts("\nError writing backplane EEPROM!\n");
783 setbpip
, 2, 1, do_set_bpip
,
784 "setbpip - Write Backplane IP-Address\n",
788 #endif /* CONFIG_CPCI405AB */