2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <fdt_support.h>
26 #include <asm/processor.h>
33 DECLARE_GLOBAL_DATA_PTR
;
35 extern int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[]);
36 extern void __ft_board_setup(void *blob
, bd_t
*bd
);
40 /* fpga configuration data - generated by bin2cc */
41 const unsigned char fpgadata
[] =
43 #if defined(CONFIG_CPCI405_VER2)
44 # if defined(CONFIG_CPCI405AB)
45 # include "fpgadata_cpci405ab.c"
47 # include "fpgadata_cpci4052.c"
50 # include "fpgadata_cpci405.c"
55 * include common fpga code (for esd boards)
57 #include "../common/fpga.c"
58 #include "../common/auto_update.h"
60 #if defined(CONFIG_CPCI405AB)
61 au_image_t au_image
[] = {
62 {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT
},
63 {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR
},
64 {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR
},
65 {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE
},
66 {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT
},
69 #if defined(CONFIG_CPCI405_VER2)
70 au_image_t au_image
[] = {
71 {"cpci4052/preinst.img", 0, -1, AU_SCRIPT
},
72 {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR
},
73 {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR
},
74 {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE
},
75 {"cpci4052/postinst.img", 0, 0, AU_SCRIPT
},
78 au_image_t au_image
[] = {
79 {"cpci405/preinst.img", 0, -1, AU_SCRIPT
},
80 {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR
},
81 {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR
},
82 {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE
},
83 {"cpci405/postinst.img", 0, 0, AU_SCRIPT
},
88 int N_AU_IMAGES
= (sizeof(au_image
) / sizeof(au_image
[0]));
91 int cpci405_version(void);
92 int gunzip(void *, int, unsigned char *, unsigned long *);
93 void lxt971_no_sleep(void);
95 int board_early_init_f(void)
97 #ifndef CONFIG_CPCI405_VER2
103 /* set up serial port with default baudrate */
105 gd
->baudrate
= CONFIG_BAUDRATE
;
111 * First pull fpga-prg pin low,
112 * to disable fpga logic (on version 2 board)
114 out_be32((void *)GPIO0_ODR
, 0x00000000); /* no open drain pins */
115 out_be32((void *)GPIO0_TCR
, CONFIG_SYS_FPGA_PRG
); /* setup for output */
116 out_be32((void *)GPIO0_OR
, CONFIG_SYS_FPGA_PRG
); /* set output pins to high */
117 out_be32((void *)GPIO0_OR
, 0); /* pull prg low */
122 #ifndef CONFIG_CPCI405_VER2
123 if (cpci405_version() == 1) {
124 status
= fpga_boot((unsigned char *)fpgadata
, sizeof(fpgadata
));
126 /* booting FPGA failed */
128 /* set up serial port with default baudrate */
130 gd
->baudrate
= CONFIG_BAUDRATE
;
134 printf("\nFPGA: Booting failed ");
136 case ERROR_FPGA_PRG_INIT_LOW
:
137 printf("(Timeout: INIT not low after "
138 "asserting PROGRAM*)\n ");
140 case ERROR_FPGA_PRG_INIT_HIGH
:
141 printf("(Timeout: INIT not high after "
142 "deasserting PROGRAM*)\n ");
144 case ERROR_FPGA_PRG_DONE
:
145 printf("(Timeout: DONE not high after "
146 "programming FPGA)\n ");
150 /* display infos on fpgaimage */
152 for (i
= 0; i
< 4; i
++) {
153 len
= fpgadata
[index
];
154 printf("FPGA: %s\n", &(fpgadata
[index
+ 1]));
159 for (i
= 20; i
> 0; i
--) {
160 printf("Rebooting in %2d seconds \r",i
);
161 for (index
= 0; index
< 1000; index
++)
165 do_reset(NULL
, 0, 0, NULL
);
168 #endif /* !CONFIG_CPCI405_VER2 */
171 * IRQ 0-15 405GP internally generated; active high; level sensitive
172 * IRQ 16 405GP internally generated; active low; level sensitive
174 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
175 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
176 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
177 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
178 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
179 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
180 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
182 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
183 mtdcr(uicer
, 0x00000000); /* disable all ints */
184 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
185 #if defined(CONFIG_CPCI405_6U)
186 if (cpci405_version() == 3) {
187 mtdcr(uicpr
, 0xFFFFFF99); /* set int polarities */
189 mtdcr(uicpr
, 0xFFFFFF81); /* set int polarities */
192 mtdcr(uicpr
, 0xFFFFFF81); /* set int polarities */
194 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
195 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,
196 * INT0 highest priority */
197 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
204 #if defined(CONFIG_CPCI405_VER2)
205 return 0; /* no, board is cpci405 */
207 if ((in_8((void*)0xf0000400) == 0x00) &&
208 (in_8((void*)0xf0000401) == 0x01))
209 return 0; /* no, board is cpci405 */
211 return -1; /* yes, board is cterm-m2 */
215 int cpci405_host(void)
217 if (mfdcr(strap
) & PSR_PCI_ARBIT_EN
)
218 return -1; /* yes, board is cpci405 host */
220 return 0; /* no, board is cpci405 adapter */
223 int cpci405_version(void)
225 unsigned long cntrl0Reg
;
229 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
231 cntrl0Reg
= mfdcr(cntrl0
);
232 mtdcr(cntrl0
, cntrl0Reg
| 0x03000000);
233 out_be32((void*)GPIO0_ODR
, in_be32((void*)GPIO0_ODR
) & ~0x00180000);
234 out_be32((void*)GPIO0_TCR
, in_be32((void*)GPIO0_TCR
) & ~0x00180000);
235 udelay(1000); /* wait some time before reading input */
236 value
= in_be32((void*)GPIO0_IR
) & 0x00180000; /* get config bits */
239 * Restore GPIO settings
241 mtdcr(cntrl0
, cntrl0Reg
);
245 /* CS2==1 && CS3==1 -> version 1 */
248 /* CS2==0 && CS3==1 -> version 2 */
251 /* CS2==1 && CS3==0 -> version 3 or 6U board */
254 /* CS2==0 && CS3==0 -> version 4 */
257 /* should not be reached! */
262 int misc_init_r (void)
264 unsigned long cntrl0Reg
;
266 /* adjust flash start and offset */
267 gd
->bd
->bi_flashstart
= 0 - gd
->bd
->bi_flashsize
;
268 gd
->bd
->bi_flashoffset
= 0;
270 #if defined(CONFIG_CPCI405_VER2)
273 ulong len
= sizeof(fpgadata
);
279 * On CPCI-405 version 2 the environment is saved in eeprom!
280 * FPGA can be gzip compressed (malloc) and booted this late.
282 if (cpci405_version() >= 2) {
284 * Setup GPIO pins (CS6+CS7 as GPIO)
286 cntrl0Reg
= mfdcr(cntrl0
);
287 mtdcr(cntrl0
, cntrl0Reg
| 0x00300000);
289 dst
= malloc(CONFIG_SYS_FPGA_MAX_SIZE
);
290 if (gunzip(dst
, CONFIG_SYS_FPGA_MAX_SIZE
,
291 (uchar
*)fpgadata
, &len
) != 0) {
292 printf("GUNZIP ERROR - must RESET board to recover\n");
293 do_reset(NULL
, 0, 0, NULL
);
296 status
= fpga_boot(dst
, len
);
298 printf("\nFPGA: Booting failed ");
300 case ERROR_FPGA_PRG_INIT_LOW
:
301 printf("(Timeout: INIT not low after "
302 "asserting PROGRAM*)\n ");
304 case ERROR_FPGA_PRG_INIT_HIGH
:
305 printf("(Timeout: INIT not high after "
306 "deasserting PROGRAM*)\n ");
308 case ERROR_FPGA_PRG_DONE
:
309 printf("(Timeout: DONE not high after "
310 "programming FPGA)\n ");
314 /* display infos on fpgaimage */
316 for (i
= 0; i
< 4; i
++) {
318 printf("FPGA: %s\n", &(dst
[index
+ 1]));
323 for (i
= 20; i
> 0; i
--) {
324 printf("Rebooting in %2d seconds \r", i
);
325 for (index
= 0; index
< 1000; index
++)
329 do_reset(NULL
, 0, 0, NULL
);
332 /* restore gpio/cs settings */
333 mtdcr(cntrl0
, cntrl0Reg
);
337 /* display infos on fpgaimage */
339 for (i
= 0; i
< 4; i
++) {
341 printf("%s ", &(dst
[index
+ 1]));
349 * Reset FPGA via FPGA_DATA pin
351 SET_FPGA(FPGA_PRG
| FPGA_CLK
);
352 udelay(1000); /* wait 1ms */
353 SET_FPGA(FPGA_PRG
| FPGA_CLK
| FPGA_DATA
);
354 udelay(1000); /* wait 1ms */
356 #if defined(CONFIG_CPCI405_6U)
357 #error HIER GETH ES WEITER MIT IO ACCESSORS
358 if (cpci405_version() == 3) {
360 * Enable outputs in fpga on version 3 board
362 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
,
363 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
) |
364 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT
);
369 out_8((void*)CONFIG_SYS_LED_ADDR
, 0x00);
372 * Reset external DUART
374 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
,
375 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
) |
376 CONFIG_SYS_FPGA_MODE_DUART_RESET
);
378 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
,
379 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
) &
380 ~CONFIG_SYS_FPGA_MODE_DUART_RESET
);
385 puts("\n*** U-Boot Version does not match Board Version!\n");
386 puts("*** CPCI-405 Version 1.x detected!\n");
387 puts("*** Please use correct U-Boot version "
388 "(CPCI405 instead of CPCI4052)!\n\n");
391 #else /* CONFIG_CPCI405_VER2 */
392 if (cpci405_version() >= 2) {
393 puts("\n*** U-Boot Version does not match Board Version!\n");
394 puts("*** CPCI-405 Board Version 2.x detected!\n");
395 puts("*** Please use correct U-Boot version "
396 "(CPCI4052 instead of CPCI405)!\n\n");
398 #endif /* CONFIG_CPCI405_VER2 */
401 * Select cts (and not dsr) on uart1
403 cntrl0Reg
= mfdcr(cntrl0
);
404 mtdcr(cntrl0
, cntrl0Reg
| 0x00001000);
410 * Check Board Identity:
415 #ifndef CONFIG_CPCI405_VER2
420 int i
= getenv_r("serial#", str
, sizeof(str
));
426 puts("### No HW ID - assuming CPCI405");
430 ver
= cpci405_version();
431 printf(" (Ver %d.x, ", ver
);
437 * Read board-id and save in env-variable
439 sprintf(str
, "%d", *(unsigned char *)0xf0000400);
440 setenv("boardid", str
);
441 printf("CTERM-M2 - Id=%s)", str
);
444 puts("PCI Host Version)");
446 puts("PCI Adapter Version)");
449 #ifndef CONFIG_CPCI405_VER2
452 /* display infos on fpgaimage */
454 for (i
= 0; i
< 4; i
++) {
455 len
= fpgadata
[index
];
456 printf("%s ", &(fpgadata
[index
+ 1]));
467 #if defined(CONFIG_LXT971_NO_SLEEP)
470 * Disable sleep mode in LXT971
476 #if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
477 void ide_set_reset(int on
)
480 * Assert or deassert CompactFlash Reset Pin
482 if (on
) { /* assert RESET */
483 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
,
484 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
) &
485 ~CONFIG_SYS_FPGA_MODE_CF_RESET
);
486 } else { /* release RESET */
487 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
,
488 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR
) |
489 CONFIG_SYS_FPGA_MODE_CF_RESET
);
493 #endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
495 #if defined(CONFIG_PCI)
496 void cpci405_pci_fixup_irq(struct pci_controller
*hose
, pci_dev_t dev
)
498 unsigned char int_line
= 0xff;
501 * Write pci interrupt line register (cpci405 specific)
503 switch (PCI_DEV(dev
) & 0x03) {
518 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
, int_line
);
521 int pci_pre_init(struct pci_controller
*hose
)
523 hose
->fixup_irq
= cpci405_pci_fixup_irq
;
526 #endif /* defined(CONFIG_PCI) */
528 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
529 void ft_board_setup(void *blob
, bd_t
*bd
)
533 __ft_board_setup(blob
, bd
);
536 * Disable PCI in adapter mode.
538 if (!cpci405_host()) {
539 rc
= fdt_find_and_setprop(blob
, "/plb/pci@ec000000", "status",
540 "disabled", sizeof("disabled"), 1);
542 printf("Unable to update property status in PCI node, "
548 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
550 #if defined(CONFIG_CPCI405AB)
551 #define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
552 CONFIG_SYS_FPGA_MODE), \
553 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
554 CONFIG_SYS_FPGA_MODE)) | \
555 CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
557 #define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
558 CONFIG_SYS_FPGA_MODE), \
559 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
560 CONFIG_SYS_FPGA_MODE)) & \
561 ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
563 #define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
564 CONFIG_SYS_FPGA_STATUS)) & \
565 CONFIG_SYS_FPGA_MODE_1WIRE)
568 * Generate a 1-wire reset, return 1 if no presence detect was found,
569 * return 0 otherwise.
570 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
572 int OWTouchReset(void)
581 result
= ONE_WIRE_GET
;
588 * Send 1 a 1-wire write bit.
589 * Provide 10us recovery time.
591 void OWWriteBit(int bit
)
613 * Read a bit from the 1-wire bus and return it.
614 * Provide 10us recovery time.
625 result
= ONE_WIRE_GET
;
631 void OWWriteByte(int data
)
635 for (loop
= 0; loop
< 8; loop
++) {
636 OWWriteBit(data
& 0x01);
643 int loop
, result
= 0;
645 for (loop
= 0; loop
< 8; loop
++) {
654 int do_onewire(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
659 unsigned char ow_id
[6];
661 unsigned char ow_crc
;
664 * Clear 1-wire bit (open drain with pull-up)
666 val
= in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR
+
667 CONFIG_SYS_FPGA_MODE
));
668 val
&= ~CONFIG_SYS_FPGA_MODE_1WIRE
; /* clear 1-wire bit */
669 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR
+
670 CONFIG_SYS_FPGA_MODE
), val
);
672 result
= OWTouchReset();
674 puts("No 1-wire device detected!\n");
676 OWWriteByte(0x33); /* send read rom command */
677 OWReadByte(); /* skip family code ( == 0x01) */
678 for (i
= 0; i
< 6; i
++)
679 ow_id
[i
] = OWReadByte();
680 ow_crc
= OWReadByte(); /* read crc */
682 sprintf(str
, "%08X%04X",
683 *(unsigned int *)&ow_id
[0],
684 *(unsigned short *)&ow_id
[4]);
685 printf("Setting environment variable 'ow_id' to %s\n", str
);
686 setenv("ow_id", str
);
691 onewire
, 1, 1, do_onewire
,
696 #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
697 #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
700 * Write backplane ip-address...
702 int do_get_bpip(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
711 buf
= malloc(CONFIG_ENV_SIZE_2
);
712 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2
, 0,
713 (uchar
*)buf
, CONFIG_ENV_SIZE_2
))
714 puts("\nError reading backplane EEPROM!\n");
716 crc
= crc32(0, (uchar
*)(buf
+4), CONFIG_ENV_SIZE_2
- 4);
717 if (crc
!= *(ulong
*)buf
) {
718 printf("ERROR: crc mismatch %08lx %08lx\n",
726 ptr
= strstr(buf
+4, "bp_ip=");
728 printf("ERROR: bp_ip not found!\n");
732 ipaddr
= string_to_ip(ptr
);
735 * Update whole ip-addr
737 bd
->bi_ip_addr
= ipaddr
;
738 sprintf(str
, "%ld.%ld.%ld.%ld",
739 (bd
->bi_ip_addr
& 0xff000000) >> 24,
740 (bd
->bi_ip_addr
& 0x00ff0000) >> 16,
741 (bd
->bi_ip_addr
& 0x0000ff00) >> 8,
742 (bd
->bi_ip_addr
& 0x000000ff));
743 setenv("ipaddr", str
);
744 printf("Updated ip_addr from bp_eeprom to %s!\n", str
);
752 getbpip
, 1, 1, do_get_bpip
,
753 "Update IP-Address with Backplane IP-Address",
758 * Set and print backplane ip...
760 int do_set_bpip(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
771 printf("Setting bp_ip to %s\n", argv
[1]);
772 buf
= malloc(CONFIG_ENV_SIZE_2
);
773 memset(buf
, 0, CONFIG_ENV_SIZE_2
);
774 sprintf(str
, "bp_ip=%s", argv
[1]);
776 crc
= crc32(0, (uchar
*)(buf
+4), CONFIG_ENV_SIZE_2
- 4);
779 if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2
,
780 0, (uchar
*)buf
, CONFIG_ENV_SIZE_2
))
781 puts("\nError writing backplane EEPROM!\n");
788 setbpip
, 2, 1, do_set_bpip
,
789 "Write Backplane IP-Address",
793 #endif /* CONFIG_CPCI405AB */