board/esd/cpci750/mv_eth.h

   1 /*
   2  * (C) Copyright 2003
   3  * Ingo Assmus <ingo.assmus@keymile.com>
   4  *
   5  * based on - Driver for MV64360X ethernet ports
   6  * Copyright (C) 2002 rabeeh@galileo.co.il
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * mv_eth.h - header file for the polled mode GT ethernet driver
  29  */
  30
  31 #ifndef __DB64360_ETH_H__
  32 #define __DB64360_ETH_H__
  33
  34 #include <asm/types.h>
  35 #include <asm/io.h>
  36 #include <asm/byteorder.h>
  37 #include <common.h>
  38 #include <net.h>
  39 #include "mv_regs.h"
  40 #include <asm/errno.h>
  41
  42
  43 /*************************************************************************
  44 **************************************************************************
  45 **************************************************************************
  46 *  The first part is the high level driver of the gigE ethernet ports.   *
  47 **************************************************************************
  48 **************************************************************************
  49 *************************************************************************/
  50 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
  51 #ifndef MAX_SKB_FRAGS
  52 #define MAX_SKB_FRAGS 0
  53 #endif
  54
  55 /* Port attributes */
  56 /*#define MAX_RX_QUEUE_NUM      8*/
  57 /*#define MAX_TX_QUEUE_NUM      8*/
  58 #define MAX_RX_QUEUE_NUM        1
  59 #define MAX_TX_QUEUE_NUM        1
  60
  61
  62 /* Use one TX queue and one RX queue */
  63 #define MV64360_TX_QUEUE_NUM 1
  64 #define MV64360_RX_QUEUE_NUM 1
  65
  66 /*
  67  * Number of RX / TX descriptors on RX / TX rings.
  68  * Note that allocating RX descriptors is done by allocating the RX
  69  * ring AND a preallocated RX buffers (skb's) for each descriptor.
  70  * The TX descriptors only allocates the TX descriptors ring,
  71  * with no pre allocated TX buffers (skb's are allocated by higher layers.
  72  */
  73
  74 /* Default TX ring size is 10 descriptors */
  75 #ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
  76 #define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
  77 #else
  78 #define MV64360_TX_QUEUE_SIZE 4
  79 #endif
  80
  81 /* Default RX ring size is 4 descriptors */
  82 #ifdef  CONFIG_MV64360_ETH_RXQUEUE_SIZE
  83 #define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
  84 #else
  85 #define MV64360_RX_QUEUE_SIZE 4
  86 #endif
  87
  88 #ifdef CONFIG_RX_BUFFER_SIZE
  89 #define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
  90 #else
  91 #define MV64360_RX_BUFFER_SIZE 1600
  92 #endif
  93
  94 #ifdef CONFIG_TX_BUFFER_SIZE
  95 #define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
  96 #else
  97 #define MV64360_TX_BUFFER_SIZE 1600
  98 #endif
  99
 100
 101 /*
 102  *      Network device statistics. Akin to the 2.0 ether stats but
 103  *      with byte counters.
 104  */
 105
 106 struct net_device_stats
 107 {
 108         unsigned long   rx_packets;             /* total packets received       */
 109         unsigned long   tx_packets;             /* total packets transmitted    */
 110         unsigned long   rx_bytes;               /* total bytes received         */
 111         unsigned long   tx_bytes;               /* total bytes transmitted      */
 112         unsigned long   rx_errors;              /* bad packets received         */
 113         unsigned long   tx_errors;              /* packet transmit problems     */
 114         unsigned long   rx_dropped;             /* no space in linux buffers    */
 115         unsigned long   tx_dropped;             /* no space available in linux  */
 116         unsigned long   multicast;              /* multicast packets received   */
 117         unsigned long   collisions;
 118
 119         /* detailed rx_errors: */
 120         unsigned long   rx_length_errors;
 121         unsigned long   rx_over_errors;         /* receiver ring buff overflow  */
 122         unsigned long   rx_crc_errors;          /* recved pkt with crc error    */
 123         unsigned long   rx_frame_errors;        /* recv'd frame alignment error */
 124         unsigned long   rx_fifo_errors;         /* recv'r fifo overrun          */
 125         unsigned long   rx_missed_errors;       /* receiver missed packet       */
 126
 127         /* detailed tx_errors */
 128         unsigned long   tx_aborted_errors;
 129         unsigned long   tx_carrier_errors;
 130         unsigned long   tx_fifo_errors;
 131         unsigned long   tx_heartbeat_errors;
 132         unsigned long   tx_window_errors;
 133
 134         /* for cslip etc */
 135         unsigned long   rx_compressed;
 136         unsigned long   tx_compressed;
 137 };
 138
 139
 140 /* Private data structure used for ethernet device */
 141 struct mv64360_eth_priv {
 142     unsigned int port_num;
 143     struct net_device_stats *stats;
 144
 145 /* to buffer area aligned */
 146     char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];    /*pointers to alligned tx buffs in memory space */
 147     char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];    /*pointers to allinged rx buffs in memory space */
 148
 149     /* Size of Tx Ring per queue */
 150     unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
 151
 152
 153     /* Size of Rx Ring per queue */
 154     unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
 155
 156     /* Magic Number for Ethernet running */
 157     unsigned int eth_running;
 158
 159 };
 160
 161
 162 int mv64360_eth_init (struct eth_device *dev);
 163 int mv64360_eth_stop (struct eth_device *dev);
 164 int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
 165 int mv64360_eth_open (struct eth_device *dev);
 166
 167
 168 /*************************************************************************
 169 **************************************************************************
 170 **************************************************************************
 171 *  The second part is the low level driver of the gigE ethernet ports.   *
 172 **************************************************************************
 173 **************************************************************************
 174 *************************************************************************/
 175
 176
 177 /********************************************************************************
 178  * Header File for : MV-643xx network interface header
 179  *
 180  * DESCRIPTION:
 181  *       This header file contains macros typedefs and function declaration for
 182  *       the Marvell Gig Bit Ethernet Controller.
 183  *
 184  * DEPENDENCIES:
 185  *       None.
 186  *
 187  *******************************************************************************/
 188
 189
 190 #ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
 191 #ifdef CONFIG_MV64360_SRAM_CACHEABLE
 192 /* In case SRAM is cacheable but not cache coherent */
 193 #define D_CACHE_FLUSH_LINE(addr, offset)       \
 194 {                   \
 195   __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
 196 }
 197 #else
 198 /* In case SRAM is cache coherent or non-cacheable */
 199 #define D_CACHE_FLUSH_LINE(addr, offset) ;
 200 #endif
 201 #else
 202 #ifdef CONFIG_NOT_COHERENT_CACHE
 203 /* In case of descriptors on DDR but not cache coherent */
 204 #define D_CACHE_FLUSH_LINE(addr, offset)       \
 205 {                   \
 206   __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
 207 }
 208 #else
 209 /* In case of descriptors on DDR and cache coherent */
 210 #define D_CACHE_FLUSH_LINE(addr, offset) ;
 211 #endif /* CONFIG_NOT_COHERENT_CACHE */
 212 #endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
 213
 214
 215 #define CPU_PIPE_FLUSH             \
 216 {                 \
 217   __asm__ __volatile__ ("eieio");         \
 218 }
 219
 220
 221 /* defines  */
 222
 223 /* Default port configuration value */
 224 #define PORT_CONFIG_VALUE                       \
 225              ETH_UNICAST_NORMAL_MODE            |   \
 226              ETH_DEFAULT_RX_QUEUE_0             |   \
 227              ETH_DEFAULT_RX_ARP_QUEUE_0         |   \
 228              ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP    |   \
 229              ETH_RECEIVE_BC_IF_IP               |   \
 230              ETH_RECEIVE_BC_IF_ARP              |   \
 231              ETH_CAPTURE_TCP_FRAMES_DIS         |   \
 232              ETH_CAPTURE_UDP_FRAMES_DIS         |   \
 233              ETH_DEFAULT_RX_TCP_QUEUE_0         |   \
 234              ETH_DEFAULT_RX_UDP_QUEUE_0         |   \
 235              ETH_DEFAULT_RX_BPDU_QUEUE_0
 236
 237 /* Default port extend configuration value */
 238 #define PORT_CONFIG_EXTEND_VALUE                \
 239              ETH_SPAN_BPDU_PACKETS_AS_NORMAL    |   \
 240              ETH_PARTITION_DISABLE
 241
 242
 243 /* Default sdma control value */
 244 #ifdef CONFIG_NOT_COHERENT_CACHE
 245 #define PORT_SDMA_CONFIG_VALUE                          \
 246                          ETH_RX_BURST_SIZE_16_64BIT     |       \
 247                          GT_ETH_IPG_INT_RX(0)                   |       \
 248                          ETH_TX_BURST_SIZE_16_64BIT;
 249 #else
 250 #define PORT_SDMA_CONFIG_VALUE                  \
 251                          ETH_RX_BURST_SIZE_4_64BIT      |       \
 252                          GT_ETH_IPG_INT_RX(0)                   |       \
 253                          ETH_TX_BURST_SIZE_4_64BIT;
 254 #endif
 255
 256 #define GT_ETH_IPG_INT_RX(value)                \
 257             ((value & 0x3fff) << 8)
 258
 259 /* Default port serial control value */
 260 #define PORT_SERIAL_CONTROL_VALUE                           \
 261                         ETH_FORCE_LINK_PASS                     |       \
 262                         ETH_ENABLE_AUTO_NEG_FOR_DUPLX           |       \
 263                         ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL      |       \
 264                         ETH_ADV_SYMMETRIC_FLOW_CTRL             |       \
 265                         ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX       |       \
 266                         ETH_FORCE_BP_MODE_NO_JAM                |       \
 267                         BIT9                                    |       \
 268                         ETH_DO_NOT_FORCE_LINK_FAIL              |       \
 269                         ETH_RETRANSMIT_16_ETTEMPTS              |       \
 270                         ETH_ENABLE_AUTO_NEG_SPEED_GMII          |       \
 271                         ETH_DTE_ADV_0                           |       \
 272                         ETH_DISABLE_AUTO_NEG_BYPASS             |       \
 273                         ETH_AUTO_NEG_NO_CHANGE                  |       \
 274                         ETH_MAX_RX_PACKET_1552BYTE              |       \
 275                         ETH_CLR_EXT_LOOPBACK                    |       \
 276                         ETH_SET_FULL_DUPLEX_MODE                |       \
 277                         ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
 278
 279 #define RX_BUFFER_MAX_SIZE  0xFFFF
 280 #define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
 281
 282 #define RX_BUFFER_MIN_SIZE  0x8
 283 #define TX_BUFFER_MIN_SIZE  0x8
 284
 285 /* Tx WRR confoguration macros */
 286 #define PORT_MAX_TRAN_UNIT          0x24    /* MTU register (default) 9KByte */
 287 #define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
 288 #define PORT_TOKEN_RATE             1023    /* PTTBRC register (default)     */
 289
 290 /* MAC accepet/reject macros */
 291 #define ACCEPT_MAC_ADDR     0
 292 #define REJECT_MAC_ADDR     1
 293
 294 /* Size of a Tx/Rx descriptor used in chain list data structure */
 295 #define RX_DESC_ALIGNED_SIZE            0x20
 296 #define TX_DESC_ALIGNED_SIZE            0x20
 297
 298 /* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
 299 #define TX_BUF_OFFSET_IN_DESC       0x18
 300 /* Buffer offset from buffer pointer */
 301 #define RX_BUF_OFFSET                           0x2
 302
 303 /* Gap define */
 304 #define ETH_BAR_GAP                                     0x8
 305 #define ETH_SIZE_REG_GAP                                0x8
 306 #define ETH_HIGH_ADDR_REMAP_REG_GAP                     0x4
 307 #define ETH_PORT_ACCESS_CTRL_GAP                        0x4
 308
 309 /* Gigabit Ethernet Unit Global Registers */
 310
 311 /* MIB Counters register definitions */
 312 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
 313 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
 314 #define ETH_MIB_BAD_OCTETS_RECEIVED        0x8
 315 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
 316 #define ETH_MIB_GOOD_FRAMES_RECEIVED       0x10
 317 #define ETH_MIB_BAD_FRAMES_RECEIVED        0x14
 318 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
 319 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
 320 #define ETH_MIB_FRAMES_64_OCTETS           0x20
 321 #define ETH_MIB_FRAMES_65_TO_127_OCTETS    0x24
 322 #define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
 323 #define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
 324 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
 325 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
 326 #define ETH_MIB_GOOD_OCTETS_SENT_LOW       0x38
 327 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH      0x3c
 328 #define ETH_MIB_GOOD_FRAMES_SENT           0x40
 329 #define ETH_MIB_EXCESSIVE_COLLISION        0x44
 330 #define ETH_MIB_MULTICAST_FRAMES_SENT      0x48
 331 #define ETH_MIB_BROADCAST_FRAMES_SENT      0x4c
 332 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
 333 #define ETH_MIB_FC_SENT                    0x54
 334 #define ETH_MIB_GOOD_FC_RECEIVED           0x58
 335 #define ETH_MIB_BAD_FC_RECEIVED            0x5c
 336 #define ETH_MIB_UNDERSIZE_RECEIVED         0x60
 337 #define ETH_MIB_FRAGMENTS_RECEIVED         0x64
 338 #define ETH_MIB_OVERSIZE_RECEIVED          0x68
 339 #define ETH_MIB_JABBER_RECEIVED            0x6c
 340 #define ETH_MIB_MAC_RECEIVE_ERROR          0x70
 341 #define ETH_MIB_BAD_CRC_EVENT              0x74
 342 #define ETH_MIB_COLLISION                  0x78
 343 #define ETH_MIB_LATE_COLLISION             0x7c
 344
 345 /* Port serial status reg (PSR) */
 346 #define ETH_INTERFACE_GMII_MII                          0
 347 #define ETH_INTERFACE_PCM                               BIT0
 348 #define ETH_LINK_IS_DOWN                                0
 349 #define ETH_LINK_IS_UP                                  BIT1
 350 #define ETH_PORT_AT_HALF_DUPLEX                         0
 351 #define ETH_PORT_AT_FULL_DUPLEX                         BIT2
 352 #define ETH_RX_FLOW_CTRL_DISABLED                       0
 353 #define ETH_RX_FLOW_CTRL_ENBALED                        BIT3
 354 #define ETH_GMII_SPEED_100_10                           0
 355 #define ETH_GMII_SPEED_1000                             BIT4
 356 #define ETH_MII_SPEED_10                                0
 357 #define ETH_MII_SPEED_100                               BIT5
 358 #define ETH_NO_TX                                       0
 359 #define ETH_TX_IN_PROGRESS                              BIT7
 360 #define ETH_BYPASS_NO_ACTIVE                            0
 361 #define ETH_BYPASS_ACTIVE                               BIT8
 362 #define ETH_PORT_NOT_AT_PARTITION_STATE                 0
 363 #define ETH_PORT_AT_PARTITION_STATE                     BIT9
 364 #define ETH_PORT_TX_FIFO_NOT_EMPTY                      0
 365 #define ETH_PORT_TX_FIFO_EMPTY                          BIT10
 366
 367
 368 /* These macros describes the Port configuration reg (Px_cR) bits */
 369 #define ETH_UNICAST_NORMAL_MODE                         0
 370 #define ETH_UNICAST_PROMISCUOUS_MODE                    BIT0
 371 #define ETH_DEFAULT_RX_QUEUE_0                          0
 372 #define ETH_DEFAULT_RX_QUEUE_1                          BIT1
 373 #define ETH_DEFAULT_RX_QUEUE_2                          BIT2
 374 #define ETH_DEFAULT_RX_QUEUE_3                          (BIT2 | BIT1)
 375 #define ETH_DEFAULT_RX_QUEUE_4                          BIT3
 376 #define ETH_DEFAULT_RX_QUEUE_5                          (BIT3 | BIT1)
 377 #define ETH_DEFAULT_RX_QUEUE_6                          (BIT3 | BIT2)
 378 #define ETH_DEFAULT_RX_QUEUE_7                          (BIT3 | BIT2 | BIT1)
 379 #define ETH_DEFAULT_RX_ARP_QUEUE_0                      0
 380 #define ETH_DEFAULT_RX_ARP_QUEUE_1                      BIT4
 381 #define ETH_DEFAULT_RX_ARP_QUEUE_2                      BIT5
 382 #define ETH_DEFAULT_RX_ARP_QUEUE_3                      (BIT5 | BIT4)
 383 #define ETH_DEFAULT_RX_ARP_QUEUE_4                      BIT6
 384 #define ETH_DEFAULT_RX_ARP_QUEUE_5                      (BIT6 | BIT4)
 385 #define ETH_DEFAULT_RX_ARP_QUEUE_6                      (BIT6 | BIT5)
 386 #define ETH_DEFAULT_RX_ARP_QUEUE_7                      (BIT6 | BIT5 | BIT4)
 387 #define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP                 0
 388 #define ETH_REJECT_BC_IF_NOT_IP_OR_ARP                  BIT7
 389 #define ETH_RECEIVE_BC_IF_IP                            0
 390 #define ETH_REJECT_BC_IF_IP                             BIT8
 391 #define ETH_RECEIVE_BC_IF_ARP                           0
 392 #define ETH_REJECT_BC_IF_ARP                            BIT9
 393 #define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY               BIT12
 394 #define ETH_CAPTURE_TCP_FRAMES_DIS                      0
 395 #define ETH_CAPTURE_TCP_FRAMES_EN                       BIT14
 396 #define ETH_CAPTURE_UDP_FRAMES_DIS                      0
 397 #define ETH_CAPTURE_UDP_FRAMES_EN                       BIT15
 398 #define ETH_DEFAULT_RX_TCP_QUEUE_0                      0
 399 #define ETH_DEFAULT_RX_TCP_QUEUE_1                      BIT16
 400 #define ETH_DEFAULT_RX_TCP_QUEUE_2                      BIT17
 401 #define ETH_DEFAULT_RX_TCP_QUEUE_3                      (BIT17 | BIT16)
 402 #define ETH_DEFAULT_RX_TCP_QUEUE_4                      BIT18
 403 #define ETH_DEFAULT_RX_TCP_QUEUE_5                      (BIT18 | BIT16)
 404 #define ETH_DEFAULT_RX_TCP_QUEUE_6                      (BIT18 | BIT17)
 405 #define ETH_DEFAULT_RX_TCP_QUEUE_7                      (BIT18 | BIT17 | BIT16)
 406 #define ETH_DEFAULT_RX_UDP_QUEUE_0                      0
 407 #define ETH_DEFAULT_RX_UDP_QUEUE_1                      BIT19
 408 #define ETH_DEFAULT_RX_UDP_QUEUE_2                      BIT20
 409 #define ETH_DEFAULT_RX_UDP_QUEUE_3                      (BIT20 | BIT19)
 410 #define ETH_DEFAULT_RX_UDP_QUEUE_4                      (BIT21
 411 #define ETH_DEFAULT_RX_UDP_QUEUE_5                      (BIT21 | BIT19)
 412 #define ETH_DEFAULT_RX_UDP_QUEUE_6                      (BIT21 | BIT20)
 413 #define ETH_DEFAULT_RX_UDP_QUEUE_7                      (BIT21 | BIT20 | BIT19)
 414 #define ETH_DEFAULT_RX_BPDU_QUEUE_0                      0
 415 #define ETH_DEFAULT_RX_BPDU_QUEUE_1                     BIT22
 416 #define ETH_DEFAULT_RX_BPDU_QUEUE_2                     BIT23
 417 #define ETH_DEFAULT_RX_BPDU_QUEUE_3                     (BIT23 | BIT22)
 418 #define ETH_DEFAULT_RX_BPDU_QUEUE_4                     BIT24
 419 #define ETH_DEFAULT_RX_BPDU_QUEUE_5                     (BIT24 | BIT22)
 420 #define ETH_DEFAULT_RX_BPDU_QUEUE_6                     (BIT24 | BIT23)
 421 #define ETH_DEFAULT_RX_BPDU_QUEUE_7                     (BIT24 | BIT23 | BIT22)
 422
 423
 424 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
 425 #define ETH_CLASSIFY_EN                                 BIT0
 426 #define ETH_SPAN_BPDU_PACKETS_AS_NORMAL                 0
 427 #define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7             BIT1
 428 #define ETH_PARTITION_DISABLE                           0
 429 #define ETH_PARTITION_ENABLE                            BIT2
 430
 431
 432 /* Tx/Rx queue command reg (RQCR/TQCR)*/
 433 #define ETH_QUEUE_0_ENABLE                              BIT0
 434 #define ETH_QUEUE_1_ENABLE                              BIT1
 435 #define ETH_QUEUE_2_ENABLE                              BIT2
 436 #define ETH_QUEUE_3_ENABLE                              BIT3
 437 #define ETH_QUEUE_4_ENABLE                              BIT4
 438 #define ETH_QUEUE_5_ENABLE                              BIT5
 439 #define ETH_QUEUE_6_ENABLE                              BIT6
 440 #define ETH_QUEUE_7_ENABLE                              BIT7
 441 #define ETH_QUEUE_0_DISABLE                             BIT8
 442 #define ETH_QUEUE_1_DISABLE                             BIT9
 443 #define ETH_QUEUE_2_DISABLE                             BIT10
 444 #define ETH_QUEUE_3_DISABLE                             BIT11
 445 #define ETH_QUEUE_4_DISABLE                             BIT12
 446 #define ETH_QUEUE_5_DISABLE                             BIT13
 447 #define ETH_QUEUE_6_DISABLE                             BIT14
 448 #define ETH_QUEUE_7_DISABLE                             BIT15
 449
 450
 451 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
 452 #define ETH_RIFB                                        BIT0
 453 #define ETH_RX_BURST_SIZE_1_64BIT                       0
 454 #define ETH_RX_BURST_SIZE_2_64BIT                       BIT1
 455 #define ETH_RX_BURST_SIZE_4_64BIT                       BIT2
 456 #define ETH_RX_BURST_SIZE_8_64BIT                       (BIT2 | BIT1)
 457 #define ETH_RX_BURST_SIZE_16_64BIT                      BIT3
 458 #define ETH_BLM_RX_NO_SWAP                              BIT4
 459 #define ETH_BLM_RX_BYTE_SWAP                            0
 460 #define ETH_BLM_TX_NO_SWAP                              BIT5
 461 #define ETH_BLM_TX_BYTE_SWAP                            0
 462 #define ETH_DESCRIPTORS_BYTE_SWAP                       BIT6
 463 #define ETH_DESCRIPTORS_NO_SWAP                         0
 464 #define ETH_TX_BURST_SIZE_1_64BIT                       0
 465 #define ETH_TX_BURST_SIZE_2_64BIT                       BIT22
 466 #define ETH_TX_BURST_SIZE_4_64BIT                       BIT23
 467 #define ETH_TX_BURST_SIZE_8_64BIT                       (BIT23 | BIT22)
 468 #define ETH_TX_BURST_SIZE_16_64BIT                      BIT24
 469
 470
 471 /* These macros describes the Port serial control reg (PSCR) bits */
 472 #define ETH_SERIAL_PORT_DISABLE                         0
 473 #define ETH_SERIAL_PORT_ENABLE                          BIT0
 474 #define ETH_FORCE_LINK_PASS                             BIT1
 475 #define ETH_DO_NOT_FORCE_LINK_PASS                      0
 476 #define ETH_ENABLE_AUTO_NEG_FOR_DUPLX                   0
 477 #define ETH_DISABLE_AUTO_NEG_FOR_DUPLX                  BIT2
 478 #define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL               0
 479 #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL              BIT3
 480 #define ETH_ADV_NO_FLOW_CTRL                            0
 481 #define ETH_ADV_SYMMETRIC_FLOW_CTRL                     BIT4
 482 #define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX               0
 483 #define ETH_FORCE_FC_MODE_TX_PAUSE_DIS                  BIT5
 484 #define ETH_FORCE_BP_MODE_NO_JAM                        0
 485 #define ETH_FORCE_BP_MODE_JAM_TX                        BIT7
 486 #define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR              BIT8
 487 #define ETH_FORCE_LINK_FAIL                             0
 488 #define ETH_DO_NOT_FORCE_LINK_FAIL                      BIT10
 489 #define ETH_RETRANSMIT_16_ETTEMPTS                      0
 490 #define ETH_RETRANSMIT_FOREVER                          BIT11
 491 #define ETH_DISABLE_AUTO_NEG_SPEED_GMII                 BIT13
 492 #define ETH_ENABLE_AUTO_NEG_SPEED_GMII                  0
 493 #define ETH_DTE_ADV_0                                   0
 494 #define ETH_DTE_ADV_1                                   BIT14
 495 #define ETH_DISABLE_AUTO_NEG_BYPASS                     0
 496 #define ETH_ENABLE_AUTO_NEG_BYPASS                      BIT15
 497 #define ETH_AUTO_NEG_NO_CHANGE                          0
 498 #define ETH_RESTART_AUTO_NEG                            BIT16
 499 #define ETH_MAX_RX_PACKET_1518BYTE                      0
 500 #define ETH_MAX_RX_PACKET_1522BYTE                      BIT17
 501 #define ETH_MAX_RX_PACKET_1552BYTE                      BIT18
 502 #define ETH_MAX_RX_PACKET_9022BYTE                      (BIT18 | BIT17)
 503 #define ETH_MAX_RX_PACKET_9192BYTE                      BIT19
 504 #define ETH_MAX_RX_PACKET_9700BYTE                      (BIT19 | BIT17)
 505 #define ETH_SET_EXT_LOOPBACK                            BIT20
 506 #define ETH_CLR_EXT_LOOPBACK                            0
 507 #define ETH_SET_FULL_DUPLEX_MODE                        BIT21
 508 #define ETH_SET_HALF_DUPLEX_MODE                        0
 509 #define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX       BIT22
 510 #define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX      0
 511 #define ETH_SET_GMII_SPEED_TO_10_100                    0
 512 #define ETH_SET_GMII_SPEED_TO_1000                      BIT23
 513 #define ETH_SET_MII_SPEED_TO_10                         0
 514 #define ETH_SET_MII_SPEED_TO_100                        BIT24
 515
 516
 517 /* SMI reg */
 518 #define ETH_SMI_BUSY            BIT28   /* 0 - Write, 1 - Read          */
 519 #define ETH_SMI_READ_VALID      BIT27   /* 0 - Write, 1 - Read          */
 520 #define ETH_SMI_OPCODE_WRITE    0       /* Completion of Read operation */
 521 #define ETH_SMI_OPCODE_READ     BIT26   /* Operation is in progress             */
 522
 523 /* SDMA command status fields macros */
 524
 525 /* Tx & Rx descriptors status */
 526 #define ETH_ERROR_SUMMARY                   (BIT0)
 527
 528 /* Tx & Rx descriptors command */
 529 #define ETH_BUFFER_OWNED_BY_DMA             (BIT31)
 530
 531 /* Tx descriptors status */
 532 #define ETH_LC_ERROR                        (0    )
 533 #define ETH_UR_ERROR                        (BIT1 )
 534 #define ETH_RL_ERROR                        (BIT2 )
 535 #define ETH_LLC_SNAP_FORMAT                 (BIT9 )
 536
 537 /* Rx descriptors status */
 538 #define ETH_CRC_ERROR                       (0    )
 539 #define ETH_OVERRUN_ERROR                   (BIT1 )
 540 #define ETH_MAX_FRAME_LENGTH_ERROR          (BIT2 )
 541 #define ETH_RESOURCE_ERROR                  ((BIT2 | BIT1))
 542 #define ETH_VLAN_TAGGED                     (BIT19)
 543 #define ETH_BPDU_FRAME                      (BIT20)
 544 #define ETH_TCP_FRAME_OVER_IP_V_4           (0    )
 545 #define ETH_UDP_FRAME_OVER_IP_V_4           (BIT21)
 546 #define ETH_OTHER_FRAME_TYPE                (BIT22)
 547 #define ETH_LAYER_2_IS_ETH_V_2              (BIT23)
 548 #define ETH_FRAME_TYPE_IP_V_4               (BIT24)
 549 #define ETH_FRAME_HEADER_OK                 (BIT25)
 550 #define ETH_RX_LAST_DESC                    (BIT26)
 551 #define ETH_RX_FIRST_DESC                   (BIT27)
 552 #define ETH_UNKNOWN_DESTINATION_ADDR        (BIT28)
 553 #define ETH_RX_ENABLE_INTERRUPT             (BIT29)
 554 #define ETH_LAYER_4_CHECKSUM_OK             (BIT30)
 555
 556 /* Rx descriptors byte count */
 557 #define ETH_FRAME_FRAGMENTED                (BIT2)
 558
 559 /* Tx descriptors command */
 560 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC         (BIT10)
 561 #define ETH_FRAME_SET_TO_VLAN               (BIT15)
 562 #define ETH_TCP_FRAME                       (0    )
 563 #define ETH_UDP_FRAME                       (BIT16)
 564 #define ETH_GEN_TCP_UDP_CHECKSUM            (BIT17)
 565 #define ETH_GEN_IP_V_4_CHECKSUM             (BIT18)
 566 #define ETH_ZERO_PADDING                    (BIT19)
 567 #define ETH_TX_LAST_DESC                    (BIT20)
 568 #define ETH_TX_FIRST_DESC                   (BIT21)
 569 #define ETH_GEN_CRC                         (BIT22)
 570 #define ETH_TX_ENABLE_INTERRUPT             (BIT23)
 571 #define ETH_AUTO_MODE                       (BIT30)
 572
 573 /* Address decode parameters */
 574 /* Ethernet Base Address Register bits */
 575 #define EBAR_TARGET_DRAM                                        0x00000000
 576 #define EBAR_TARGET_DEVICE                                      0x00000001
 577 #define EBAR_TARGET_CBS                                         0x00000002
 578 #define EBAR_TARGET_PCI0                                        0x00000003
 579 #define EBAR_TARGET_PCI1                                        0x00000004
 580 #define EBAR_TARGET_CUNIT                                       0x00000005
 581 #define EBAR_TARGET_AUNIT                                       0x00000006
 582 #define EBAR_TARGET_GUNIT                                       0x00000007
 583
 584 /* Window attributes */
 585 #define EBAR_ATTR_DRAM_CS0                                      0x00000E00
 586 #define EBAR_ATTR_DRAM_CS1                                      0x00000D00
 587 #define EBAR_ATTR_DRAM_CS2                                      0x00000B00
 588 #define EBAR_ATTR_DRAM_CS3                                      0x00000700
 589
 590 /* DRAM Target interface */
 591 #define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY       0x00000000
 592 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT       0x00001000
 593 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB       0x00002000
 594
 595 /* Device Bus Target interface */
 596 #define EBAR_ATTR_DEVICE_DEVCS0                         0x00001E00
 597 #define EBAR_ATTR_DEVICE_DEVCS1                         0x00001D00
 598 #define EBAR_ATTR_DEVICE_DEVCS2                         0x00001B00
 599 #define EBAR_ATTR_DEVICE_DEVCS3                         0x00001700
 600 #define EBAR_ATTR_DEVICE_BOOTCS3                        0x00000F00
 601
 602 /* PCI Target interface */
 603 #define EBAR_ATTR_PCI_BYTE_SWAP                         0x00000000
 604 #define EBAR_ATTR_PCI_NO_SWAP                           0x00000100
 605 #define EBAR_ATTR_PCI_BYTE_WORD_SWAP            0x00000200
 606 #define EBAR_ATTR_PCI_WORD_SWAP                         0x00000300
 607 #define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT       0x00000000
 608 #define EBAR_ATTR_PCI_NO_SNOOP_ASSERT           0x00000400
 609 #define EBAR_ATTR_PCI_IO_SPACE                          0x00000000
 610 #define EBAR_ATTR_PCI_MEMORY_SPACE                      0x00000800
 611 #define EBAR_ATTR_PCI_REQ64_FORCE                       0x00000000
 612 #define EBAR_ATTR_PCI_REQ64_SIZE                        0x00001000
 613
 614 /* CPU 60x bus or internal SRAM interface */
 615 #define EBAR_ATTR_CBS_SRAM_BLOCK0                       0x00000000
 616 #define EBAR_ATTR_CBS_SRAM_BLOCK1                       0x00000100
 617 #define EBAR_ATTR_CBS_SRAM                                      0x00000000
 618 #define EBAR_ATTR_CBS_CPU_BUS                           0x00000800
 619
 620 /* Window access control */
 621 #define EWIN_ACCESS_NOT_ALLOWED 0
 622 #define EWIN_ACCESS_READ_ONLY   BIT0
 623 #define EWIN_ACCESS_FULL        (BIT1 | BIT0)
 624 #define EWIN0_ACCESS_MASK               0x0003
 625 #define EWIN1_ACCESS_MASK               0x000C
 626 #define EWIN2_ACCESS_MASK               0x0030
 627 #define EWIN3_ACCESS_MASK               0x00C0
 628
 629 /* typedefs */
 630
 631 typedef enum _eth_port
 632 {
 633     ETH_0 = 0,
 634         ETH_1 = 1,
 635         ETH_2 = 2
 636 }ETH_PORT;
 637
 638 typedef enum _eth_func_ret_status
 639 {
 640     ETH_OK,                     /* Returned as expected.                    */
 641     ETH_ERROR,                  /* Fundamental error.                       */
 642     ETH_RETRY,                  /* Could not process request. Try later.    */
 643     ETH_END_OF_JOB,             /* Ring has nothing to process.             */
 644     ETH_QUEUE_FULL,             /* Ring resource error.                     */
 645     ETH_QUEUE_LAST_RESOURCE     /* Ring resources about to exhaust.         */
 646 }ETH_FUNC_RET_STATUS;
 647
 648 typedef enum _eth_queue
 649 {
 650         ETH_Q0 = 0,
 651         ETH_Q1 = 1,
 652         ETH_Q2 = 2,
 653         ETH_Q3 = 3,
 654         ETH_Q4 = 4,
 655         ETH_Q5 = 5,
 656         ETH_Q6 = 6,
 657     ETH_Q7 = 7
 658 } ETH_QUEUE;
 659
 660 typedef enum _addr_win
 661 {
 662         ETH_WIN0,
 663         ETH_WIN1,
 664         ETH_WIN2,
 665         ETH_WIN3,
 666         ETH_WIN4,
 667     ETH_WIN5
 668 } ETH_ADDR_WIN;
 669
 670 typedef enum _eth_target
 671 {
 672         ETH_TARGET_DRAM  ,
 673         ETH_TARGET_DEVICE,
 674         ETH_TARGET_CBS   ,
 675         ETH_TARGET_PCI0  ,
 676         ETH_TARGET_PCI1
 677 }ETH_TARGET;
 678
 679 typedef struct _eth_rx_desc
 680 {
 681         unsigned short  byte_cnt           ;    /* Descriptor buffer byte count     */
 682         unsigned short  buf_size           ;    /* Buffer size                      */
 683         unsigned int    cmd_sts    ;    /* Descriptor command status        */
 684         unsigned int    next_desc_ptr;    /* Next descriptor pointer          */
 685         unsigned int    buf_ptr    ;    /* Descriptor buffer pointer        */
 686     unsigned int    return_info ;    /* User resource return information */
 687 } ETH_RX_DESC;
 688
 689
 690 typedef struct _eth_tx_desc
 691 {
 692     unsigned short  byte_cnt       ;    /* Descriptor buffer byte count     */
 693     unsigned short  l4i_chk        ;    /* CPU provided TCP Checksum        */
 694     unsigned int    cmd_sts        ;    /* Descriptor command status        */
 695     unsigned int    next_desc_ptr;    /* Next descriptor pointer          */
 696     unsigned int    buf_ptr        ;    /* Descriptor buffer pointer        */
 697     unsigned int    return_info ;    /* User resource return information */
 698 } ETH_TX_DESC;
 699
 700 /* Unified struct for Rx and Tx operations. The user is not required to */
 701 /* be familier with neither Tx nor Rx descriptors.                       */
 702 typedef struct _pkt_info
 703 {
 704         unsigned short  byte_cnt   ;    /* Descriptor buffer byte count     */
 705         unsigned short  l4i_chk    ;    /* Tx CPU provided TCP Checksum     */
 706         unsigned int    cmd_sts    ;    /* Descriptor command status        */
 707         unsigned int    buf_ptr    ;    /* Descriptor buffer pointer        */
 708     unsigned int    return_info ;    /* User resource return information */
 709 } PKT_INFO;
 710
 711
 712 typedef struct _eth_win_param
 713 {
 714     ETH_ADDR_WIN win;   /* Window number. See ETH_ADDR_WIN enum */
 715     ETH_TARGET  target;    /* System targets. See ETH_TARGET enum */
 716     unsigned short attributes;  /* BAR attributes. See above macros. */
 717     unsigned int base_addr; /* Window base address in unsigned int form */
 718     unsigned int high_addr; /* Window high address in unsigned int form */
 719     unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
 720     bool enable; /* Enable/disable access to the window. */
 721     unsigned short access_ctrl; /* Access ctrl register. see above macros */
 722 } ETH_WIN_PARAM;
 723
 724
 725 /* Ethernet port specific infomation */
 726
 727 typedef struct _eth_port_ctrl
 728 {
 729     ETH_PORT  port_num; /* User Ethernet port number */
 730     int port_phy_addr;  /* User phy address of Ethrnet port */
 731     unsigned char port_mac_addr[6]; /* User defined port MAC address. */
 732     unsigned int  port_config; /* User port configuration value */
 733     unsigned int  port_config_extend; /* User port config extend value */
 734     unsigned int  port_sdma_config; /* User port SDMA config value */
 735     unsigned int  port_serial_control; /* User port serial control value */
 736     unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
 737     unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
 738
 739     /* User function to cast virtual address to CPU bus address */
 740     unsigned int  (*port_virt_to_phys)(unsigned int addr);
 741     /* User scratch pad for user specific data structures */
 742     void *port_private;
 743
 744     bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
 745     bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
 746
 747     /* Tx/Rx rings managment indexes fields. For driver use */
 748
 749     /* Next available Rx resource */
 750     volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
 751     /* Returning Rx resource */
 752     volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
 753
 754     /* Next available Tx resource */
 755     volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
 756     /* Returning Tx resource */
 757     volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
 758     /* An extra Tx index to support transmit of multiple buffers per packet */
 759     volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
 760
 761     /* Tx/Rx rings size and base variables fields. For driver use */
 762
 763     volatile ETH_RX_DESC        *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
 764     unsigned int                 rx_desc_area_size[MAX_RX_QUEUE_NUM];
 765     char                        *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
 766
 767     volatile ETH_TX_DESC        *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
 768     unsigned int                 tx_desc_area_size[MAX_TX_QUEUE_NUM];
 769     char                        *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
 770
 771 } ETH_PORT_INFO;
 772
 773
 774 /* ethernet.h API list */
 775
 776 /* Port operation control routines */
 777 static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
 778 static void eth_port_reset(ETH_PORT     eth_port_num);
 779 static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
 780
 781
 782 /* Port MAC address routines */
 783 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
 784                                   unsigned char *p_addr,
 785                                   ETH_QUEUE queue);
 786 #if 0   /* FIXME */
 787 static void eth_port_mc_addr    (ETH_PORT eth_port_num,
 788                                  unsigned char *p_addr,
 789                                  ETH_QUEUE queue,
 790                                  int option);
 791 #endif
 792
 793 /* PHY and MIB routines */
 794 static bool ethernet_phy_reset(ETH_PORT eth_port_num);
 795
 796 static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
 797                                    unsigned int phy_reg,
 798                                    unsigned int value);
 799
 800 static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
 801                                   unsigned int phy_reg,
 802                                   unsigned int* value);
 803
 804 static void eth_clear_mib_counters(ETH_PORT     eth_port_num);
 805
 806 /* Port data flow control routines */
 807 static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
 808                                              ETH_QUEUE tx_queue,
 809                                              PKT_INFO *p_pkt_info);
 810 static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
 811                                               ETH_QUEUE tx_queue,
 812                                               PKT_INFO *p_pkt_info);
 813 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
 814                                              ETH_QUEUE rx_queue,
 815                                              PKT_INFO *p_pkt_info);
 816 static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
 817                                               ETH_QUEUE rx_queue,
 818                                               PKT_INFO *p_pkt_info);
 819
 820
 821 static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
 822                                     ETH_QUEUE   tx_queue,
 823                                     int                         tx_desc_num,
 824                                     int                         tx_buff_size,
 825                                     unsigned int        tx_desc_base_addr,
 826                                     unsigned int        tx_buff_base_addr);
 827
 828 static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
 829                                     ETH_QUEUE   rx_queue,
 830                                     int                         rx_desc_num,
 831                                     int                         rx_buff_size,
 832                                     unsigned int        rx_desc_base_addr,
 833                                     unsigned int        rx_buff_base_addr);
 834
 835 #endif /* MV64360_ETH_ */