3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
7 /* PCI.c - PCI functions */
14 #include "../../Marvell/include/pci.h"
17 #undef IDE_SET_NATIVE_MODE
18 static unsigned int local_buses
[] = { 0, 0 };
20 static const unsigned char pci_irq_swizzle
[2][PCI_MAX_DEVICES
] = {
21 {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES
- 1] = 0 },
22 {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES
- 1] = 0 },
25 #ifdef CONFIG_USE_CPCIDVI
31 static GT_CPCIDVI_ROM_T gt_cpcidvi_rom
= {0, 0};
35 static const unsigned int pci_bus_list
[] = { PCI_0_MODE
, PCI_1_MODE
};
36 static void gt_pci_bus_mode_display (PCI_HOST host
)
41 mode
= (GTREGREAD (pci_bus_list
[host
]) & (BIT4
| BIT5
)) >> 4;
44 printf ("PCI %d bus mode: Conventional PCI\n", host
);
47 printf ("PCI %d bus mode: 66 MHz PCIX\n", host
);
50 printf ("PCI %d bus mode: 100 MHz PCIX\n", host
);
53 printf ("PCI %d bus mode: 133 MHz PCIX\n", host
);
56 printf ("Unknown BUS %d\n", mode
);
61 static const unsigned int pci_p2p_configuration_reg
[] = {
62 PCI_0P2P_CONFIGURATION
, PCI_1P2P_CONFIGURATION
65 static const unsigned int pci_configuration_address
[] = {
66 PCI_0CONFIGURATION_ADDRESS
, PCI_1CONFIGURATION_ADDRESS
69 static const unsigned int pci_configuration_data
[] = {
70 PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER
,
71 PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
74 static const unsigned int pci_error_cause_reg
[] = {
75 PCI_0ERROR_CAUSE
, PCI_1ERROR_CAUSE
78 static const unsigned int pci_arbiter_control
[] = {
79 PCI_0ARBITER_CONTROL
, PCI_1ARBITER_CONTROL
82 static const unsigned int pci_address_space_en
[] = {
83 PCI_0_BASE_ADDR_REG_ENABLE
, PCI_1_BASE_ADDR_REG_ENABLE
86 static const unsigned int pci_snoop_control_base_0_low
[] = {
87 PCI_0SNOOP_CONTROL_BASE_0_LOW
, PCI_1SNOOP_CONTROL_BASE_0_LOW
89 static const unsigned int pci_snoop_control_top_0
[] = {
90 PCI_0SNOOP_CONTROL_TOP_0
, PCI_1SNOOP_CONTROL_TOP_0
93 static const unsigned int pci_access_control_base_0_low
[] = {
94 PCI_0ACCESS_CONTROL_BASE_0_LOW
, PCI_1ACCESS_CONTROL_BASE_0_LOW
96 static const unsigned int pci_access_control_top_0
[] = {
97 PCI_0ACCESS_CONTROL_TOP_0
, PCI_1ACCESS_CONTROL_TOP_0
100 static const unsigned int pci_scs_bank_size
[2][4] = {
101 {PCI_0SCS_0_BANK_SIZE
, PCI_0SCS_1_BANK_SIZE
,
102 PCI_0SCS_2_BANK_SIZE
, PCI_0SCS_3_BANK_SIZE
},
103 {PCI_1SCS_0_BANK_SIZE
, PCI_1SCS_1_BANK_SIZE
,
104 PCI_1SCS_2_BANK_SIZE
, PCI_1SCS_3_BANK_SIZE
}
107 static const unsigned int pci_p2p_configuration
[] = {
108 PCI_0P2P_CONFIGURATION
, PCI_1P2P_CONFIGURATION
112 /********************************************************************
113 * pciWriteConfigReg - Write to a PCI configuration register
114 * - Make sure the GT is configured as a master before writing
115 * to another device on the PCI.
116 * - The function takes care of Big/Little endian conversion.
119 * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
120 * (or any other PCI device spec)
121 * pciDevNum: The device number needs to be addressed.
123 * Configuration Address 0xCF8:
125 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
126 * |congif|Reserved| Bus |Device|Function|Register|00|
127 * |Enable| |Number|Number| Number | Number | | <=field Name
129 *********************************************************************/
130 void pciWriteConfigReg (PCI_HOST host
, unsigned int regOffset
,
131 unsigned int pciDevNum
, unsigned int data
)
133 volatile unsigned int DataForAddrReg
;
134 unsigned int functionNum
;
135 unsigned int busNum
= 0;
138 if (pciDevNum
> 32) /* illegal device Number */
140 if (pciDevNum
== SELF
) { /* configure our configuration space. */
142 (GTREGREAD (pci_p2p_configuration_reg
[host
]) >> 24) &
144 busNum
= GTREGREAD (pci_p2p_configuration_reg
[host
]) &
147 functionNum
= regOffset
& 0x00000700;
148 pciDevNum
= pciDevNum
<< 11;
149 regOffset
= regOffset
& 0xfc;
151 (regOffset
| pciDevNum
| functionNum
| busNum
) | BIT31
;
152 GT_REG_WRITE (pci_configuration_address
[host
], DataForAddrReg
);
153 GT_REG_READ (pci_configuration_address
[host
], &addr
);
154 if (addr
!= DataForAddrReg
)
156 GT_REG_WRITE (pci_configuration_data
[host
], data
);
159 /********************************************************************
160 * pciReadConfigReg - Read from a PCI0 configuration register
161 * - Make sure the GT is configured as a master before reading
162 * from another device on the PCI.
163 * - The function takes care of Big/Little endian conversion.
164 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
166 * pciDevNum: The device number needs to be addressed.
167 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
168 * cause register to make sure the data is valid
170 * Configuration Address 0xCF8:
172 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
173 * |congif|Reserved| Bus |Device|Function|Register|00|
174 * |Enable| |Number|Number| Number | Number | | <=field Name
176 *********************************************************************/
177 unsigned int pciReadConfigReg (PCI_HOST host
, unsigned int regOffset
,
178 unsigned int pciDevNum
)
180 volatile unsigned int DataForAddrReg
;
182 unsigned int functionNum
;
183 unsigned int busNum
= 0;
185 if (pciDevNum
> 32) /* illegal device Number */
187 if (pciDevNum
== SELF
) { /* configure our configuration space. */
189 (GTREGREAD (pci_p2p_configuration_reg
[host
]) >> 24) &
191 busNum
= GTREGREAD (pci_p2p_configuration_reg
[host
]) &
194 functionNum
= regOffset
& 0x00000700;
195 pciDevNum
= pciDevNum
<< 11;
196 regOffset
= regOffset
& 0xfc;
198 (regOffset
| pciDevNum
| functionNum
| busNum
) | BIT31
;
199 GT_REG_WRITE (pci_configuration_address
[host
], DataForAddrReg
);
200 GT_REG_READ (pci_configuration_address
[host
], &data
);
201 if (data
!= DataForAddrReg
)
203 GT_REG_READ (pci_configuration_data
[host
], &data
);
207 /********************************************************************
208 * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
209 * the agent is placed on another Bus. For more
210 * information read P2P in the PCI spec.
212 * Inputs: unsigned int regOffset - The register offset as it apears in the
213 * GT spec (or any other PCI device spec).
214 * unsigned int pciDevNum - The device number needs to be addressed.
215 * unsigned int busNum - On which bus does the Target agent connect
217 * unsigned int data - data to be written.
219 * Configuration Address 0xCF8:
221 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
222 * |congif|Reserved| Bus |Device|Function|Register|01|
223 * |Enable| |Number|Number| Number | Number | | <=field Name
225 * The configuration Address is configure as type-I (bits[1:0] = '01') due to
226 * PCI spec referring to P2P.
228 *********************************************************************/
229 void pciOverBridgeWriteConfigReg (PCI_HOST host
,
230 unsigned int regOffset
,
231 unsigned int pciDevNum
,
232 unsigned int busNum
, unsigned int data
)
234 unsigned int DataForReg
;
235 unsigned int functionNum
;
237 functionNum
= regOffset
& 0x00000700;
238 pciDevNum
= pciDevNum
<< 11;
239 regOffset
= regOffset
& 0xff;
240 busNum
= busNum
<< 16;
241 if (pciDevNum
== SELF
) { /* This board */
242 DataForReg
= (regOffset
| pciDevNum
| functionNum
) | BIT0
;
244 DataForReg
= (regOffset
| pciDevNum
| functionNum
| busNum
) |
247 GT_REG_WRITE (pci_configuration_address
[host
], DataForReg
);
248 GT_REG_WRITE (pci_configuration_data
[host
], data
);
252 /********************************************************************
253 * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
254 * the agent target locate on another PCI bus.
255 * - Make sure the GT is configured as a master
256 * before reading from another device on the PCI.
257 * - The function takes care of Big/Little endian
259 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
260 * spec). (configuration register offset.)
261 * pciDevNum: The device number needs to be addressed.
262 * busNum: the Bus number where the agent is place.
263 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
264 * cause register to make sure the data is valid
266 * Configuration Address 0xCF8:
268 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
269 * |congif|Reserved| Bus |Device|Function|Register|01|
270 * |Enable| |Number|Number| Number | Number | | <=field Name
272 *********************************************************************/
273 unsigned int pciOverBridgeReadConfigReg (PCI_HOST host
,
274 unsigned int regOffset
,
275 unsigned int pciDevNum
,
278 unsigned int DataForReg
;
280 unsigned int functionNum
;
282 functionNum
= regOffset
& 0x00000700;
283 pciDevNum
= pciDevNum
<< 11;
284 regOffset
= regOffset
& 0xff;
285 busNum
= busNum
<< 16;
286 if (pciDevNum
== SELF
) { /* This board */
287 DataForReg
= (regOffset
| pciDevNum
| functionNum
) | BIT31
;
288 } else { /* agent on another bus */
290 DataForReg
= (regOffset
| pciDevNum
| functionNum
| busNum
) |
293 GT_REG_WRITE (pci_configuration_address
[host
], DataForReg
);
294 GT_REG_READ (pci_configuration_data
[host
], &data
);
299 /********************************************************************
300 * pciGetRegOffset - Gets the register offset for this region config.
302 * INPUT: Bus, Region - The bus and region we ask for its base address.
304 * RETURNS: PCI register base address
305 *********************************************************************/
306 static unsigned int pciGetRegOffset (PCI_HOST host
, PCI_REGION region
)
312 return PCI_0I_O_LOW_DECODE_ADDRESS
;
314 return PCI_0MEMORY0_LOW_DECODE_ADDRESS
;
316 return PCI_0MEMORY1_LOW_DECODE_ADDRESS
;
318 return PCI_0MEMORY2_LOW_DECODE_ADDRESS
;
320 return PCI_0MEMORY3_LOW_DECODE_ADDRESS
;
325 return PCI_1I_O_LOW_DECODE_ADDRESS
;
327 return PCI_1MEMORY0_LOW_DECODE_ADDRESS
;
329 return PCI_1MEMORY1_LOW_DECODE_ADDRESS
;
331 return PCI_1MEMORY2_LOW_DECODE_ADDRESS
;
333 return PCI_1MEMORY3_LOW_DECODE_ADDRESS
;
336 return PCI_0MEMORY0_LOW_DECODE_ADDRESS
;
339 static unsigned int pciGetRemapOffset (PCI_HOST host
, PCI_REGION region
)
345 return PCI_0I_O_ADDRESS_REMAP
;
347 return PCI_0MEMORY0_ADDRESS_REMAP
;
349 return PCI_0MEMORY1_ADDRESS_REMAP
;
351 return PCI_0MEMORY2_ADDRESS_REMAP
;
353 return PCI_0MEMORY3_ADDRESS_REMAP
;
358 return PCI_1I_O_ADDRESS_REMAP
;
360 return PCI_1MEMORY0_ADDRESS_REMAP
;
362 return PCI_1MEMORY1_ADDRESS_REMAP
;
364 return PCI_1MEMORY2_ADDRESS_REMAP
;
366 return PCI_1MEMORY3_ADDRESS_REMAP
;
369 return PCI_0MEMORY0_ADDRESS_REMAP
;
372 /********************************************************************
373 * pciGetBaseAddress - Gets the base address of a PCI.
374 * - If the PCI size is 0 then this base address has no meaning!!!
377 * INPUT: Bus, Region - The bus and region we ask for its base address.
379 * RETURNS: PCI base address.
380 *********************************************************************/
381 unsigned int pciGetBaseAddress (PCI_HOST host
, PCI_REGION region
)
383 unsigned int regBase
;
385 unsigned int regOffset
= pciGetRegOffset (host
, region
);
387 GT_REG_READ (regOffset
, ®Base
);
388 GT_REG_READ (regOffset
+ 8, ®End
);
390 if (regEnd
<= regBase
)
391 return 0xffffffff; /* ERROR !!! */
393 regBase
= regBase
<< 16;
397 bool pciMapSpace (PCI_HOST host
, PCI_REGION region
, unsigned int remapBase
,
398 unsigned int bankBase
, unsigned int bankLength
)
400 unsigned int low
= 0xfff;
401 unsigned int high
= 0x0;
402 unsigned int regOffset
= pciGetRegOffset (host
, region
);
403 unsigned int remapOffset
= pciGetRemapOffset (host
, region
);
405 if (bankLength
!= 0) {
406 low
= (bankBase
>> 16) & 0xffff;
407 high
= ((bankBase
+ bankLength
) >> 16) - 1;
410 GT_REG_WRITE (regOffset
, low
| (1 << 24)); /* no swapping */
411 GT_REG_WRITE (regOffset
+ 8, high
);
413 if (bankLength
!= 0) { /* must do AFTER writing maps */
414 GT_REG_WRITE (remapOffset
, remapBase
>> 16); /* sorry, 32 bits only.
415 dont support upper 32
421 unsigned int pciGetSpaceBase (PCI_HOST host
, PCI_REGION region
)
424 unsigned int regOffset
= pciGetRegOffset (host
, region
);
426 GT_REG_READ (regOffset
, &low
);
427 return (low
& 0xffff) << 16;
430 unsigned int pciGetSpaceSize (PCI_HOST host
, PCI_REGION region
)
432 unsigned int low
, high
;
433 unsigned int regOffset
= pciGetRegOffset (host
, region
);
435 GT_REG_READ (regOffset
, &low
);
436 GT_REG_READ (regOffset
+ 8, &high
);
437 return ((high
& 0xffff) + 1) << 16;
441 /* ronen - 7/Dec/03*/
442 /********************************************************************
443 * gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
444 * Inputs: one of the PCI BAR
445 *********************************************************************/
446 void gtPciEnableInternalBAR (PCI_HOST host
, PCI_INTERNAL_BAR pciBAR
)
448 RESET_REG_BITS (pci_address_space_en
[host
], BIT0
<< pciBAR
);
451 void gtPciDisableInternalBAR (PCI_HOST host
, PCI_INTERNAL_BAR pciBAR
)
453 SET_REG_BITS (pci_address_space_en
[host
], BIT0
<< pciBAR
);
456 /********************************************************************
457 * pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
459 * Inputs: base and size of PCI SCS
460 *********************************************************************/
461 void pciMapMemoryBank (PCI_HOST host
, MEMORY_BANK bank
,
462 unsigned int pciDramBase
, unsigned int pciDramSize
)
464 /*ronen different function for 3rd bank. */
465 unsigned int offset
= (bank
< 2) ? bank
* 8 : 0x100 + (bank
- 2) * 8;
467 pciDramBase
= pciDramBase
& 0xfffff000;
468 pciDramBase
= pciDramBase
| (pciReadConfigReg (host
,
469 PCI_SCS_0_BASE_ADDRESS
472 pciWriteConfigReg (host
, PCI_SCS_0_BASE_ADDRESS
+ offset
, SELF
,
474 if (pciDramSize
== 0)
476 GT_REG_WRITE (pci_scs_bank_size
[host
][bank
], pciDramSize
- 1);
477 gtPciEnableInternalBAR (host
, bank
);
480 /********************************************************************
481 * pciSetRegionFeatures - This function modifys one of the 8 regions with
482 * feature bits given as an input.
483 * - Be advised to check the spec before modifying them.
484 * Inputs: PCI_PROTECT_REGION region - one of the eight regions.
485 * unsigned int features - See file: pci.h there are defintion for those
487 * unsigned int baseAddress - The region base Address.
488 * unsigned int topAddress - The region top Address.
489 * Returns: false if one of the parameters is erroneous true otherwise.
490 *********************************************************************/
491 bool pciSetRegionFeatures (PCI_HOST host
, PCI_ACCESS_REGIONS region
,
492 unsigned int features
, unsigned int baseAddress
,
493 unsigned int regionLength
)
495 unsigned int accessLow
;
496 unsigned int accessHigh
;
497 unsigned int accessTop
= baseAddress
+ regionLength
;
499 if (regionLength
== 0) { /* close the region. */
500 pciDisableAccessRegion (host
, region
);
503 /* base Address is store is bits [11:0] */
504 accessLow
= (baseAddress
& 0xfff00000) >> 20;
505 /* All the features are update according to the defines in pci.h (to be on
506 the safe side we disable bits: [11:0] */
507 accessLow
= accessLow
| (features
& 0xfffff000);
508 /* write to the Low Access Region register */
509 GT_REG_WRITE (pci_access_control_base_0_low
[host
] + 0x10 * region
,
512 accessHigh
= (accessTop
& 0xfff00000) >> 20;
514 /* write to the High Access Region register */
515 GT_REG_WRITE (pci_access_control_top_0
[host
] + 0x10 * region
,
520 /********************************************************************
521 * pciDisableAccessRegion - Disable The given Region by writing MAX size
522 * to its low Address and MIN size to its high Address.
524 * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
526 *********************************************************************/
527 void pciDisableAccessRegion (PCI_HOST host
, PCI_ACCESS_REGIONS region
)
529 /* writing back the registers default values. */
530 GT_REG_WRITE (pci_access_control_base_0_low
[host
] + 0x10 * region
,
532 GT_REG_WRITE (pci_access_control_top_0
[host
] + 0x10 * region
, 0);
535 /********************************************************************
536 * pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
540 *********************************************************************/
541 bool pciArbiterEnable (PCI_HOST host
)
543 unsigned int regData
;
545 GT_REG_READ (pci_arbiter_control
[host
], ®Data
);
546 GT_REG_WRITE (pci_arbiter_control
[host
], regData
| BIT31
);
550 /********************************************************************
551 * pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
555 *********************************************************************/
556 bool pciArbiterDisable (PCI_HOST host
)
558 unsigned int regData
;
560 GT_REG_READ (pci_arbiter_control
[host
], ®Data
);
561 GT_REG_WRITE (pci_arbiter_control
[host
], regData
& 0x7fffffff);
565 /********************************************************************
566 * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
568 * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
569 * PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
570 * PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
571 * PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
572 * PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
573 * PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
574 * PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
576 *********************************************************************/
577 bool pciSetArbiterAgentsPriority (PCI_HOST host
, PCI_AGENT_PRIO internalAgent
,
578 PCI_AGENT_PRIO externalAgent0
,
579 PCI_AGENT_PRIO externalAgent1
,
580 PCI_AGENT_PRIO externalAgent2
,
581 PCI_AGENT_PRIO externalAgent3
,
582 PCI_AGENT_PRIO externalAgent4
,
583 PCI_AGENT_PRIO externalAgent5
)
585 unsigned int regData
;
586 unsigned int writeData
;
588 GT_REG_READ (pci_arbiter_control
[host
], ®Data
);
589 writeData
= (internalAgent
<< 7) + (externalAgent0
<< 8) +
590 (externalAgent1
<< 9) + (externalAgent2
<< 10) +
591 (externalAgent3
<< 11) + (externalAgent4
<< 12) +
592 (externalAgent5
<< 13);
593 regData
= (regData
& 0xffffc07f) | writeData
;
594 GT_REG_WRITE (pci_arbiter_control
[host
], regData
& regData
);
598 /********************************************************************
599 * pciParkingDisable - Park on last option disable, with this function you can
600 * disable the park on last mechanism for each agent.
601 * disabling this option for all agents results parking
602 * on the internal master.
604 * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
605 * PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
606 * PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
607 * PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
608 * PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
609 * PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
610 * PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
612 *********************************************************************/
613 bool pciParkingDisable (PCI_HOST host
, PCI_AGENT_PARK internalAgent
,
614 PCI_AGENT_PARK externalAgent0
,
615 PCI_AGENT_PARK externalAgent1
,
616 PCI_AGENT_PARK externalAgent2
,
617 PCI_AGENT_PARK externalAgent3
,
618 PCI_AGENT_PARK externalAgent4
,
619 PCI_AGENT_PARK externalAgent5
)
621 unsigned int regData
;
622 unsigned int writeData
;
624 GT_REG_READ (pci_arbiter_control
[host
], ®Data
);
625 writeData
= (internalAgent
<< 14) + (externalAgent0
<< 15) +
626 (externalAgent1
<< 16) + (externalAgent2
<< 17) +
627 (externalAgent3
<< 18) + (externalAgent4
<< 19) +
628 (externalAgent5
<< 20);
629 regData
= (regData
& ~(0x7f << 14)) | writeData
;
630 GT_REG_WRITE (pci_arbiter_control
[host
], regData
);
634 /********************************************************************
635 * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
636 * respond to grant assertion within a window specified in
637 * the input value: 'brokenValue'.
639 * Inputs: unsigned char brokenValue - A value which limits the Master to hold the
640 * grant without asserting frame.
641 * Returns: Error for illegal broken value otherwise true.
642 *********************************************************************/
643 bool pciEnableBrokenAgentDetection (PCI_HOST host
, unsigned char brokenValue
)
646 unsigned int regData
;
648 if (brokenValue
> 0xf)
649 return false; /* brokenValue must be 4 bit */
650 data
= brokenValue
<< 3;
651 GT_REG_READ (pci_arbiter_control
[host
], ®Data
);
652 regData
= (regData
& 0xffffff87) | data
;
653 GT_REG_WRITE (pci_arbiter_control
[host
], regData
| BIT1
);
657 /********************************************************************
658 * pciDisableBrokenAgentDetection - This function disable the Broken agent
659 * Detection mechanism.
660 * NOTE: This operation may cause a dead lock on the
665 *********************************************************************/
666 bool pciDisableBrokenAgentDetection (PCI_HOST host
)
668 unsigned int regData
;
670 GT_REG_READ (pci_arbiter_control
[host
], ®Data
);
671 regData
= regData
& 0xfffffffd;
672 GT_REG_WRITE (pci_arbiter_control
[host
], regData
);
676 /********************************************************************
677 * pciP2PConfig - This function set the PCI_n P2P configurate.
678 * For more information on the P2P read PCI spec.
680 * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
682 * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
684 * unsigned int busNum - The CPI bus number to which the PCI interface
686 * unsigned int devNum - The PCI interface's device number.
689 *********************************************************************/
690 bool pciP2PConfig (PCI_HOST host
, unsigned int SecondBusLow
,
691 unsigned int SecondBusHigh
,
692 unsigned int busNum
, unsigned int devNum
)
694 unsigned int regData
;
696 regData
= (SecondBusLow
& 0xff) | ((SecondBusHigh
& 0xff) << 8) |
697 ((busNum
& 0xff) << 16) | ((devNum
& 0x1f) << 24);
698 GT_REG_WRITE (pci_p2p_configuration
[host
], regData
);
702 /********************************************************************
703 * pciSetRegionSnoopMode - This function modifys one of the 4 regions which
704 * supports Cache Coherency in the PCI_n interface.
705 * Inputs: region - One of the four regions.
706 * snoopType - There is four optional Types:
708 * 2. Snoop to WT region.
709 * 3. Snoop to WB region.
710 * 4. Snoop & Invalidate to WB region.
711 * baseAddress - Base Address of this region.
712 * regionLength - Region length.
713 * Returns: false if one of the parameters is wrong otherwise return true.
714 *********************************************************************/
715 bool pciSetRegionSnoopMode (PCI_HOST host
, PCI_SNOOP_REGION region
,
716 PCI_SNOOP_TYPE snoopType
,
717 unsigned int baseAddress
,
718 unsigned int regionLength
)
720 unsigned int snoopXbaseAddress
;
721 unsigned int snoopXtopAddress
;
723 unsigned int snoopHigh
= baseAddress
+ regionLength
;
725 if ((region
> PCI_SNOOP_REGION3
) || (snoopType
> PCI_SNOOP_WB
))
728 pci_snoop_control_base_0_low
[host
] + 0x10 * region
;
729 snoopXtopAddress
= pci_snoop_control_top_0
[host
] + 0x10 * region
;
730 if (regionLength
== 0) { /* closing the region */
731 GT_REG_WRITE (snoopXbaseAddress
, 0x0000ffff);
732 GT_REG_WRITE (snoopXtopAddress
, 0);
735 baseAddress
= baseAddress
& 0xfff00000; /* Granularity of 1MByte */
736 data
= (baseAddress
>> 20) | snoopType
<< 12;
737 GT_REG_WRITE (snoopXbaseAddress
, data
);
738 snoopHigh
= (snoopHigh
& 0xfff00000) >> 20;
739 GT_REG_WRITE (snoopXtopAddress
, snoopHigh
- 1);
743 static int gt_read_config_dword (struct pci_controller
*hose
,
744 pci_dev_t dev
, int offset
, u32
* value
)
746 int bus
= PCI_BUS (dev
);
748 if ((bus
== local_buses
[0]) || (bus
== local_buses
[1])) {
749 *value
= pciReadConfigReg ((PCI_HOST
) hose
->cfg_addr
,
750 offset
| (PCI_FUNC(dev
) << 8),
753 *value
= pciOverBridgeReadConfigReg ((PCI_HOST
) hose
->cfg_addr
,
754 offset
| (PCI_FUNC(dev
) << 8),
761 static int gt_write_config_dword (struct pci_controller
*hose
,
762 pci_dev_t dev
, int offset
, u32 value
)
764 int bus
= PCI_BUS (dev
);
766 if ((bus
== local_buses
[0]) || (bus
== local_buses
[1])) {
767 pciWriteConfigReg ((PCI_HOST
) hose
->cfg_addr
,
768 offset
| (PCI_FUNC(dev
) << 8),
769 PCI_DEV (dev
), value
);
771 pciOverBridgeWriteConfigReg ((PCI_HOST
) hose
->cfg_addr
,
772 offset
| (PCI_FUNC(dev
) << 8),
780 static void gt_setup_ide (struct pci_controller
*hose
,
781 pci_dev_t dev
, struct pci_config_table
*entry
)
783 static const int ide_bar
[] = { 8, 4, 8, 4, 0, 0 };
784 u32 bar_response
, bar_value
;
787 if (CPCI750_SLAVE_TEST
!= 0)
790 for (bar
= 0; bar
< 6; bar
++) {
791 /*ronen different function for 3rd bank. */
792 unsigned int offset
=
793 (bar
< 2) ? bar
* 8 : 0x100 + (bar
- 2) * 8;
795 pci_hose_write_config_dword (hose
, dev
, PCI_BASE_ADDRESS_0
+ offset
,
797 pci_hose_read_config_dword (hose
, dev
, PCI_BASE_ADDRESS_0
+ offset
,
800 pciauto_region_allocate (bar_response
&
801 PCI_BASE_ADDRESS_SPACE_IO
? hose
->
802 pci_io
: hose
->pci_mem
, ide_bar
[bar
],
805 pci_hose_write_config_dword (hose
, dev
, PCI_BASE_ADDRESS_0
+ bar
* 4,
810 #ifdef CONFIG_USE_CPCIDVI
811 static void gt_setup_cpcidvi (struct pci_controller
*hose
,
812 pci_dev_t dev
, struct pci_config_table
*entry
)
814 u32 bar_value
, pci_response
;
816 if (CPCI750_SLAVE_TEST
!= 0)
819 pci_hose_read_config_dword (hose
, dev
, PCI_COMMAND
, &pci_response
);
820 pci_hose_write_config_dword (hose
, dev
, PCI_BASE_ADDRESS_0
, 0xffffffff);
821 pci_hose_read_config_dword (hose
, dev
, PCI_BASE_ADDRESS_0
, &pci_response
);
822 pciauto_region_allocate (hose
->pci_mem
, 0x01000000, &bar_value
);
823 pci_hose_write_config_dword (hose
, dev
, PCI_BASE_ADDRESS_0
, (bar_value
& 0xffffff00));
824 pci_hose_write_config_dword (hose
, dev
, PCI_ROM_ADDRESS
, 0x0);
825 pciauto_region_allocate (hose
->pci_mem
, 0x40000, &bar_value
);
826 pci_hose_write_config_dword (hose
, dev
, PCI_ROM_ADDRESS
, (bar_value
& 0xffffff00) | 0x01);
827 gt_cpcidvi_rom
.base
= bar_value
& 0xffffff00;
828 gt_cpcidvi_rom
.init
= 1;
831 unsigned char gt_cpcidvi_in8(unsigned int offset
)
835 if (gt_cpcidvi_rom
.init
== 0) {
838 data
= in8((offset
& 0x04) + 0x3f000 + gt_cpcidvi_rom
.base
);
842 void gt_cpcidvi_out8(unsigned int offset
, unsigned char data
)
846 if (gt_cpcidvi_rom
.init
== 0) {
850 off
= ((off
<< 3) & 0x7f8) + (offset
& 0x4) + 0x3e000 + gt_cpcidvi_rom
.base
;
856 /* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
857 /* and is curently not called *. */
859 static void gt_fixup_irq (struct pci_controller
*hose
, pci_dev_t dev
)
861 unsigned char pin
, irq
;
863 pci_read_config_byte (dev
, PCI_INTERRUPT_PIN
, &pin
);
865 if (pin
== 1) { /* only allow INT A */
866 irq
= pci_irq_swizzle
[(PCI_HOST
) hose
->
867 cfg_addr
][PCI_DEV (dev
)];
869 pci_write_config_byte (dev
, PCI_INTERRUPT_LINE
, irq
);
874 struct pci_config_table gt_config_table
[] = {
875 #ifdef CONFIG_USE_CPCIDVI
876 {PCI_VENDOR_ID_CT
, PCI_DEVICE_ID_CT_69030
, PCI_CLASS_DISPLAY_VGA
,
877 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, gt_setup_cpcidvi
},
879 {PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_STORAGE_IDE
,
880 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, gt_setup_ide
},
884 struct pci_controller pci0_hose
= {
885 /* fixup_irq: gt_fixup_irq, */
886 config_table
:gt_config_table
,
889 struct pci_controller pci1_hose
= {
890 /* fixup_irq: gt_fixup_irq, */
891 config_table
:gt_config_table
,
894 void pci_init_board (void)
896 unsigned int command
;
898 #ifdef CONFIG_PCI_PNP
902 gt_pci_bus_mode_display (PCI_HOST0
);
904 #ifdef CONFIG_USE_CPCIDVI
905 gt_cpcidvi_rom
.init
= 0;
906 gt_cpcidvi_rom
.base
= 0;
909 slave
= CPCI750_SLAVE_TEST
;
911 pci0_hose
.config_table
= gt_config_table
;
912 pci1_hose
.config_table
= gt_config_table
;
914 #ifdef CONFIG_USE_CPCIDVI
915 gt_config_table
[0].config_device
= gt_setup_cpcidvi
;
917 gt_config_table
[1].config_device
= gt_setup_ide
;
919 pci0_hose
.first_busno
= 0;
920 pci0_hose
.last_busno
= 0xff;
921 local_buses
[0] = pci0_hose
.first_busno
;
923 /* PCI memory space */
924 pci_set_region (pci0_hose
.regions
+ 0,
925 CONFIG_SYS_PCI0_0_MEM_SPACE
,
926 CONFIG_SYS_PCI0_0_MEM_SPACE
,
927 CONFIG_SYS_PCI0_MEM_SIZE
, PCI_REGION_MEM
);
930 pci_set_region (pci0_hose
.regions
+ 1,
931 CONFIG_SYS_PCI0_IO_SPACE_PCI
,
932 CONFIG_SYS_PCI0_IO_SPACE
, CONFIG_SYS_PCI0_IO_SIZE
, PCI_REGION_IO
);
934 pci_set_ops (&pci0_hose
,
935 pci_hose_read_config_byte_via_dword
,
936 pci_hose_read_config_word_via_dword
,
937 gt_read_config_dword
,
938 pci_hose_write_config_byte_via_dword
,
939 pci_hose_write_config_word_via_dword
,
940 gt_write_config_dword
);
941 pci0_hose
.region_count
= 2;
943 pci0_hose
.cfg_addr
= (unsigned int *) PCI_HOST0
;
945 pci_register_hose (&pci0_hose
);
947 pciArbiterEnable (PCI_HOST0
);
948 pciParkingDisable (PCI_HOST0
, 1, 1, 1, 1, 1, 1, 1);
949 command
= pciReadConfigReg (PCI_HOST0
, PCI_COMMAND
, SELF
);
950 command
|= PCI_COMMAND_MASTER
;
951 pciWriteConfigReg (PCI_HOST0
, PCI_COMMAND
, SELF
, command
);
952 command
= pciReadConfigReg (PCI_HOST0
, PCI_COMMAND
, SELF
);
953 command
|= PCI_COMMAND_MEMORY
;
954 pciWriteConfigReg (PCI_HOST0
, PCI_COMMAND
, SELF
, command
);
956 #ifdef CONFIG_PCI_PNP
957 pciauto_config_init(&pci0_hose
);
958 pciauto_region_allocate(pci0_hose
.pci_io
, 0x400, &bar
);
960 #ifdef CONFIG_PCI_SCAN_SHOW
961 printf("PCI: Bus Dev VenId DevId Class Int\n");
963 pci0_hose
.last_busno
= pci_hose_scan_bus (&pci0_hose
,
964 pci0_hose
.first_busno
);
967 gt_pci_bus_mode_display (PCI_HOST1
);
970 pciArbiterDisable (PCI_HOST0
);
971 pciParkingDisable (PCI_HOST0
, 1, 1, 1, 1, 1, 1, 1);
972 command
= pciReadConfigReg (PCI_HOST0
, PCI_COMMAND
, SELF
);
973 command
|= PCI_COMMAND_MASTER
;
974 pciWriteConfigReg (PCI_HOST0
, PCI_COMMAND
, SELF
, command
);
975 command
= pciReadConfigReg (PCI_HOST0
, PCI_COMMAND
, SELF
);
976 command
|= PCI_COMMAND_MEMORY
;
977 pciWriteConfigReg (PCI_HOST0
, PCI_COMMAND
, SELF
, command
);
978 pci0_hose
.last_busno
= pci0_hose
.first_busno
;
980 pci1_hose
.first_busno
= pci0_hose
.last_busno
+ 1;
981 pci1_hose
.last_busno
= 0xff;
982 pci1_hose
.current_busno
= pci1_hose
.first_busno
;
983 local_buses
[1] = pci1_hose
.first_busno
;
985 /* PCI memory space */
986 pci_set_region (pci1_hose
.regions
+ 0,
987 CONFIG_SYS_PCI1_0_MEM_SPACE
,
988 CONFIG_SYS_PCI1_0_MEM_SPACE
,
989 CONFIG_SYS_PCI1_MEM_SIZE
, PCI_REGION_MEM
);
992 pci_set_region (pci1_hose
.regions
+ 1,
993 CONFIG_SYS_PCI1_IO_SPACE_PCI
,
994 CONFIG_SYS_PCI1_IO_SPACE
, CONFIG_SYS_PCI1_IO_SIZE
, PCI_REGION_IO
);
996 pci_set_ops (&pci1_hose
,
997 pci_hose_read_config_byte_via_dword
,
998 pci_hose_read_config_word_via_dword
,
999 gt_read_config_dword
,
1000 pci_hose_write_config_byte_via_dword
,
1001 pci_hose_write_config_word_via_dword
,
1002 gt_write_config_dword
);
1004 pci1_hose
.region_count
= 2;
1006 pci1_hose
.cfg_addr
= (unsigned int *) PCI_HOST1
;
1008 pci_register_hose (&pci1_hose
);
1010 pciArbiterEnable (PCI_HOST1
);
1011 pciParkingDisable (PCI_HOST1
, 1, 1, 1, 1, 1, 1, 1);
1013 command
= pciReadConfigReg (PCI_HOST1
, PCI_COMMAND
, SELF
);
1014 command
|= PCI_COMMAND_MASTER
;
1015 pciWriteConfigReg (PCI_HOST1
, PCI_COMMAND
, SELF
, command
);
1017 #ifdef CONFIG_PCI_PNP
1018 pciauto_config_init(&pci1_hose
);
1019 pciauto_region_allocate(pci1_hose
.pci_io
, 0x400, &bar
);
1021 pci1_hose
.last_busno
= pci_hose_scan_bus (&pci1_hose
, pci1_hose
.first_busno
);
1023 command
= pciReadConfigReg (PCI_HOST1
, PCI_COMMAND
, SELF
);
1024 command
|= PCI_COMMAND_MEMORY
;
1025 pciWriteConfigReg (PCI_HOST1
, PCI_COMMAND
, SELF
, command
);
1028 #endif /* of CONFIG_PCI */