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git.ipfire.org Git - people/ms/u-boot.git/blob - board/esd/dp405/dp405.c
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 /* fpga configuration data - not compressed, generated by bin2c */
31 const unsigned char fpgadata
[] =
35 int filesize
= sizeof(fpgadata
);
38 int board_early_init_f (void)
41 * IRQ 0-15 405GP internally generated; active high; level sensitive
42 * IRQ 16 405GP internally generated; active low; level sensitive
44 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
45 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
46 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
47 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
48 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
49 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
50 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
52 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
53 mtdcr(uicer
, 0x00000000); /* disable all ints */
54 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
55 mtdcr(uicpr
, 0xFFFFFF80); /* set int polarities */
56 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
57 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority*/
58 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
61 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
63 mtebc (epcr
, 0xa8400000); /* ebc always driven */
66 * Reset CPLD via GPIO13 (CS4) pin
68 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~(0x80000000 >> 13));
69 udelay(1000); /* wait 1ms */
70 out32(GPIO0_OR
, in32(GPIO0_OR
) | (0x80000000 >> 13));
71 udelay(1000); /* wait 1ms */
77 /* ------------------------------------------------------------------------- */
79 int misc_init_f (void)
81 return 0; /* dummy implementation */
85 int misc_init_r (void)
87 DECLARE_GLOBAL_DATA_PTR
;
89 /* adjust flash start and offset */
90 gd
->bd
->bi_flashstart
= 0 - gd
->bd
->bi_flashsize
;
91 gd
->bd
->bi_flashoffset
= 0;
98 * Check Board Identity:
101 int checkboard (void)
104 int i
= getenv_r ("serial#", str
, sizeof(str
));
105 unsigned char trans
[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
106 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
107 unsigned char id1
, id2
;
112 puts ("### No HW ID - assuming DP405");
117 id1
= trans
[(~(in32(GPIO0_IR
) >> 5)) & 0x0000000f];
118 id2
= trans
[(~(in32(GPIO0_IR
) >> 9)) & 0x0000000f];
119 printf(" (ID=0x%1X%1X, PLD=0x%02X)\n", id2
, id1
, in8(0xf0001000));
124 /* ------------------------------------------------------------------------- */
126 long int initdram (int board_type
)
130 mtdcr(memcfga
, mem_mb0cf
);
131 val
= mfdcr(memcfgd
);
134 printf("\nmb0cf=%x\n", val
); /* test-only */
135 printf("strap=%x\n", mfdcr(strap
)); /* test-only */
138 return (4*1024*1024 << ((val
& 0x000e0000) >> 17));
141 /* ------------------------------------------------------------------------- */
145 /* TODO: XXX XXX XXX */
146 printf ("test: 16 MB - ok\n");