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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
[people/ms/u-boot.git] / board / esd / du440 / du440.c
1 /*
2 * (C) Copyright 2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21 #include <common.h>
22 #include <asm/processor.h>
23 #include <asm/io.h>
24 #include <asm/bitops.h>
25 #include <command.h>
26 #include <i2c.h>
27 #include <ppc440.h>
28 #include "du440.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
33 extern ulong flash_get_size (ulong base, int banknum);
34
35 int usbhub_init(void);
36 int dvi_init(void);
37 int eeprom_write_enable (unsigned dev_addr, int state);
38 int board_revision(void);
39
40 static int du440_post_errors;
41
42 int board_early_init_f(void)
43 {
44 u32 sdr0_cust0;
45 u32 sdr0_pfc1, sdr0_pfc2;
46 u32 reg;
47
48 mtdcr(ebccfga, xbcfg);
49 mtdcr(ebccfgd, 0xb8400000);
50
51 /*
52 * Setup the GPIO pins
53 */
54 out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP);
55 out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP);
56 out_be32((void*)GPIO0_OSRL, 0x50055400);
57 out_be32((void*)GPIO0_OSRH, 0x550050aa);
58 out_be32((void*)GPIO0_TSRL, 0x50055400);
59 out_be32((void*)GPIO0_TSRH, 0x55005000);
60 out_be32((void*)GPIO0_ISR1L, 0x50000000);
61 out_be32((void*)GPIO0_ISR1H, 0x00000000);
62 out_be32((void*)GPIO0_ISR2L, 0x00000000);
63 out_be32((void*)GPIO0_ISR2H, 0x00000100);
64 out_be32((void*)GPIO0_ISR3L, 0x00000000);
65 out_be32((void*)GPIO0_ISR3H, 0x00000000);
66
67 out_be32((void*)GPIO1_OR, 0x00000000);
68 out_be32((void*)GPIO1_TCR, 0xc2000000 |
69 CFG_GPIO1_IORSTN |
70 CFG_GPIO1_LEDUSR1 |
71 CFG_GPIO1_LEDUSR2 |
72 CFG_GPIO1_LEDPOST |
73 CFG_GPIO1_LEDDU);
74 out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
75
76 out_be32((void*)GPIO1_OSRL, 0x5c280000);
77 out_be32((void*)GPIO1_OSRH, 0x00000000);
78 out_be32((void*)GPIO1_TSRL, 0x0c000000);
79 out_be32((void*)GPIO1_TSRH, 0x00000000);
80 out_be32((void*)GPIO1_ISR1L, 0x00005550);
81 out_be32((void*)GPIO1_ISR1H, 0x00000000);
82 out_be32((void*)GPIO1_ISR2L, 0x00050000);
83 out_be32((void*)GPIO1_ISR2H, 0x00000000);
84 out_be32((void*)GPIO1_ISR3L, 0x01400000);
85 out_be32((void*)GPIO1_ISR3H, 0x00000000);
86
87 /*
88 * Setup the interrupt controller polarities, triggers, etc.
89 */
90 mtdcr(uic0sr, 0xffffffff); /* clear all */
91 mtdcr(uic0er, 0x00000000); /* disable all */
92 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
93 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
94 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
95 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
96 mtdcr(uic0sr, 0xffffffff); /* clear all */
97
98 /*
99 * UIC1:
100 * bit30: ext. Irq 1: PLD : int 32+30
101 */
102 mtdcr(uic1sr, 0xffffffff); /* clear all */
103 mtdcr(uic1er, 0x00000000); /* disable all */
104 mtdcr(uic1cr, 0x00000000); /* all non-critical */
105 mtdcr(uic1pr, 0xfffffffd);
106 mtdcr(uic1tr, 0x00000000);
107 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
108 mtdcr(uic1sr, 0xffffffff); /* clear all */
109
110 /*
111 * UIC2
112 * bit3: ext. Irq 2: DCF77 : int 64+3
113 */
114 mtdcr(uic2sr, 0xffffffff); /* clear all */
115 mtdcr(uic2er, 0x00000000); /* disable all */
116 mtdcr(uic2cr, 0x00000000); /* all non-critical */
117 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
118 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
119 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
120 mtdcr(uic2sr, 0xffffffff); /* clear all */
121
122 /* select Ethernet pins */
123 mfsdr(SDR0_PFC1, sdr0_pfc1);
124 mfsdr(SDR0_PFC2, sdr0_pfc2);
125
126 /* setup EMAC bridge interface */
127 if (board_revision() == 0) {
128 /* 1 x MII */
129 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
130 SDR0_PFC1_SELECT_CONFIG_1_2;
131 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
132 SDR0_PFC2_SELECT_CONFIG_1_2;
133 } else {
134 /* 2 x SMII */
135 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
136 SDR0_PFC1_SELECT_CONFIG_6;
137 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
138 SDR0_PFC2_SELECT_CONFIG_6;
139 }
140
141 /* enable 2nd IIC */
142 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
143
144 mtsdr(SDR0_PFC2, sdr0_pfc2);
145 mtsdr(SDR0_PFC1, sdr0_pfc1);
146
147 /* PCI arbiter enabled */
148 mfsdr(sdr_pci0, reg);
149 mtsdr(sdr_pci0, 0x80000000 | reg);
150
151 /* setup NAND FLASH */
152 mfsdr(SDR0_CUST0, sdr0_cust0);
153 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
154 SDR0_CUST0_NDFC_ENABLE |
155 SDR0_CUST0_NDFC_BW_8_BIT |
156 SDR0_CUST0_NDFC_ARE_MASK |
157 (0x80000000 >> (28 + CFG_NAND0_CS)) |
158 (0x80000000 >> (28 + CFG_NAND1_CS));
159 mtsdr(SDR0_CUST0, sdr0_cust0);
160
161 return 0;
162 }
163
164 int misc_init_r(void)
165 {
166 uint pbcr;
167 int size_val = 0;
168 u32 reg;
169 unsigned long usb2d0cr = 0;
170 unsigned long usb2phy0cr, usb2h0cr = 0;
171 unsigned long sdr0_pfc1;
172 int i, j;
173
174 /* adjust flash start and offset */
175 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
176 gd->bd->bi_flashoffset = 0;
177
178 mtdcr(ebccfga, pb0cr);
179 pbcr = mfdcr(ebccfgd);
180 size_val = ffs(gd->bd->bi_flashsize) - 21;
181 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
182 mtdcr(ebccfga, pb0cr);
183 mtdcr(ebccfgd, pbcr);
184
185 /*
186 * Re-check to get correct base address
187 */
188 flash_get_size(gd->bd->bi_flashstart, 0);
189
190 /*
191 * USB suff...
192 */
193 /* SDR Setting */
194 mfsdr(SDR0_PFC1, sdr0_pfc1);
195 mfsdr(SDR0_USB0, usb2d0cr);
196 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
197 mfsdr(SDR0_USB2H0CR, usb2h0cr);
198
199 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
200 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
201 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
202 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
203 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
204 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
205 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
206 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
207 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
208 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
209
210 /* An 8-bit/60MHz interface is the only possible alternative
211 when connecting the Device to the PHY */
212 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
213 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
214
215 /* To enable the USB 2.0 Device function through the UTMI interface */
216 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
217
218 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
219 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
220
221 mtsdr(SDR0_PFC1, sdr0_pfc1);
222 mtsdr(SDR0_USB0, usb2d0cr);
223 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
224 mtsdr(SDR0_USB2H0CR, usb2h0cr);
225
226 /* clear resets */
227 udelay (1000);
228 mtsdr(SDR0_SRST1, 0x00000000);
229 udelay (1000);
230 mtsdr(SDR0_SRST0, 0x00000000);
231
232 printf("USB: Host(int phy)\n");
233
234 /*
235 * Clear PLB4A0_ACR[WRP]
236 * This fix will make the MAL burst disabling patch for the Linux
237 * EMAC driver obsolete.
238 */
239 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
240 mtdcr(plb4_acr, reg);
241
242 /*
243 * release IO-RST#
244 * We have to wait at least 560ms until we may call usbhub_init
245 */
246 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN);
247
248 /*
249 * flash USR1/2 LEDs (600ms)
250 * This results in the necessary delay from IORST# until
251 * calling usbhub_init will succeed
252 */
253 for (j = 0; j < 3; j++) {
254 out_be32((void*)GPIO1_OR,
255 (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) |
256 CFG_GPIO1_LEDUSR1);
257
258 for (i = 0; i < 100; i++)
259 udelay(1000);
260
261 out_be32((void*)GPIO1_OR,
262 (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) |
263 CFG_GPIO1_LEDUSR2);
264
265 for (i = 0; i < 100; i++)
266 udelay(1000);
267 }
268
269 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
270 ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2));
271
272 if (usbhub_init())
273 du440_post_errors++;
274
275 if (dvi_init())
276 du440_post_errors++;
277
278 return 0;
279 }
280
281 int pld_revision(void)
282 {
283 out8(CFG_CPLD_BASE, 0x00);
284 return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK);
285 }
286
287 int board_revision(void)
288 {
289 int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK)
290 >> CFG_GPIO1_HWVER_SHIFT);
291
292 return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
293 ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
294 }
295
296 #if defined(CONFIG_SHOW_ACTIVITY)
297 void board_show_activity (ulong timestamp)
298 {
299 if ((timestamp % 100) == 0)
300 out_be32((void*)GPIO1_OR,
301 in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1);
302 }
303
304 void show_activity(int arg)
305 {
306 }
307 #endif /* CONFIG_SHOW_ACTIVITY */
308
309 int du440_phy_addr(int devnum)
310 {
311 if (board_revision() == 0)
312 return devnum;
313
314 return devnum + 1;
315 }
316
317 int checkboard(void)
318 {
319 char serno[32];
320
321 puts("Board: DU440");
322
323 if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
324 puts(", serial# ");
325 puts(serno);
326 }
327
328 printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
329 board_revision(), pld_revision());
330 return (0);
331 }
332
333 /*
334 * pci_pre_init
335 *
336 * This routine is called just prior to registering the hose and gives
337 * the board the opportunity to check things. Returning a value of zero
338 * indicates that things are bad & PCI initialization should be aborted.
339 *
340 * Different boards may wish to customize the pci controller structure
341 * (add regions, override default access routines, etc) or perform
342 * certain pre-initialization actions.
343 */
344 #if defined(CONFIG_PCI)
345 int pci_pre_init(struct pci_controller *hose)
346 {
347 unsigned long addr;
348
349 /*
350 * Set priority for all PLB3 devices to 0.
351 * Set PLB3 arbiter to fair mode.
352 */
353 mfsdr(sdr_amp1, addr);
354 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
355 addr = mfdcr(plb3_acr);
356 mtdcr(plb3_acr, addr | 0x80000000);
357
358 /*
359 * Set priority for all PLB4 devices to 0.
360 */
361 mfsdr(sdr_amp0, addr);
362 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
363 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
364 mtdcr(plb4_acr, addr);
365
366 /*
367 * Set Nebula PLB4 arbiter to fair mode.
368 */
369 /* Segment0 */
370 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
371 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
372 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
373 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
374 mtdcr(plb0_acr, addr);
375
376 /* Segment1 */
377 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
378 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
379 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
380 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
381 mtdcr(plb1_acr, addr);
382
383 return 1;
384 }
385 #endif /* defined(CONFIG_PCI) */
386
387 /*
388 * pci_target_init
389 *
390 * The bootstrap configuration provides default settings for the pci
391 * inbound map (PIM). But the bootstrap config choices are limited and
392 * may not be sufficient for a given board.
393 */
394 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
395 void pci_target_init(struct pci_controller *hose)
396 {
397 /*
398 * Set up Direct MMIO registers
399 */
400 /*
401 * PowerPC440EPX PCI Master configuration.
402 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
403 * PLB address 0xA0000000-0xDFFFFFFF
404 * ==> PCI address 0xA0000000-0xDFFFFFFF
405 * Use byte reversed out routines to handle endianess.
406 * Make this region non-prefetchable.
407 */
408 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
409 /* - disabled b4 setting */
410 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
411 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
412 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
413 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
414 /* and enable region */
415
416 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
417 /* - disabled b4 setting */
418 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
419 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
420 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
421 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
422 /* and enable region */
423
424 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
425 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
426 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
427 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
428
429 /*
430 * Set up Configuration registers
431 */
432
433 /* Program the board's subsystem id/vendor id */
434 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
435 PCI_VENDOR_ID_ESDGMBH);
436 pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
437
438 pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
439
440 /* Configure command register as bus master */
441 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
442
443 /* 240nS PCI clock */
444 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
445
446 /* No error reporting */
447 pci_write_config_word(0, PCI_ERREN, 0);
448
449 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
450
451 }
452 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
453
454 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
455 void pci_master_init(struct pci_controller *hose)
456 {
457 unsigned short temp_short;
458
459 /*
460 * Write the PowerPC440 EP PCI Configuration regs.
461 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
462 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
463 */
464 pci_read_config_word(0, PCI_COMMAND, &temp_short);
465 pci_write_config_word(0, PCI_COMMAND,
466 temp_short | PCI_COMMAND_MASTER |
467 PCI_COMMAND_MEMORY);
468 }
469 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
470
471 /*
472 * is_pci_host
473 *
474 * This routine is called to determine if a pci scan should be
475 * performed. With various hardware environments (especially cPCI and
476 * PPMC) it's insufficient to depend on the state of the arbiter enable
477 * bit in the strap register, or generic host/adapter assumptions.
478 *
479 * Rather than hard-code a bad assumption in the general 440 code, the
480 * 440 pci code requires the board to decide at runtime.
481 *
482 * Return 0 for adapter mode, non-zero for host (monarch) mode.
483 */
484 #if defined(CONFIG_PCI)
485 int is_pci_host(struct pci_controller *hose)
486 {
487 /* always configured as host. */
488 return (1);
489 }
490 #endif /* defined(CONFIG_PCI) */
491
492 int last_stage_init(void)
493 {
494 int e, i;
495
496 /* everyting is ok: turn on POST-LED */
497 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
498
499 /* slowly blink on errors and finally keep LED off */
500 for (e = 0; e < du440_post_errors; e++) {
501 out_be32((void*)GPIO1_OR,
502 in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
503
504 for (i = 0; i < 500; i++)
505 udelay(1000);
506
507 out_be32((void*)GPIO1_OR,
508 in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST);
509
510 for (i = 0; i < 500; i++)
511 udelay(1000);
512 }
513
514 return 0;
515 }
516
517 #if defined(CONFIG_I2C_MULTI_BUS)
518 /*
519 * read field strength from I2C ADC
520 */
521 int dcf77_status(void)
522 {
523 unsigned int oldbus;
524 uchar u[2];
525 int mv;
526
527 oldbus = I2C_GET_BUS();
528 I2C_SET_BUS(1);
529
530 if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
531 I2C_SET_BUS(oldbus);
532 return -1;
533 }
534
535 mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
536
537 I2C_SET_BUS(oldbus);
538 return mv;
539 }
540
541 int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
542 {
543 int mv;
544 u32 pin, pinold;
545 unsigned long long t1, t2;
546 bd_t *bd = gd->bd;
547
548 printf("DCF77: ");
549 mv = dcf77_status();
550 if (mv > 0)
551 printf("signal=%d mV\n", mv);
552 else
553 printf("ERROR - no signal\n");
554
555 t1 = t2 = 0;
556 pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
557 while (!ctrlc()) {
558 pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
559 if (pin && !pinold) { /* bit start */
560 t1 = get_ticks();
561 if (t2 && ((unsigned int)(t1 - t2) /
562 (bd->bi_procfreq / 1000) >= 1800))
563 printf("Start of minute\n");
564
565 t2 = t1;
566 }
567 if (t1 && !pin && pinold) { /* bit end */
568 printf("%5d\n", (unsigned int)(get_ticks() - t1) /
569 (bd->bi_procfreq / 1000));
570 }
571 pinold = pin;
572 }
573
574 printf("Abort\n");
575 return 0;
576 }
577 U_BOOT_CMD(
578 dcf77, 1, 1, do_dcf77,
579 "dcf77 - Check DCF77 receiver\n",
580 NULL
581 );
582
583 /*
584 * initialize USB hub via I2C1
585 */
586 int usbhub_init(void)
587 {
588 int reg;
589 int ret = 0;
590 unsigned int oldbus;
591 uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
592 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
593 0x32};
594 uchar stcd;
595
596 printf("Hub: ");
597
598 oldbus = I2C_GET_BUS();
599 I2C_SET_BUS(1);
600
601 for (reg = 0; reg < sizeof(u); reg++)
602 if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
603 ret = -1;
604 break;
605 }
606
607 if (ret == 0) {
608 stcd = 0x03;
609 if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
610 ret = -1;
611 }
612
613 if (ret == 0)
614 printf("initialized\n");
615 else
616 printf("failed - cannot initialize USB hub\n");
617
618 I2C_SET_BUS(oldbus);
619 return ret;
620 }
621
622 int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
623 {
624 usbhub_init();
625 return 0;
626 }
627 U_BOOT_CMD(
628 hubinit, 1, 1, do_hubinit,
629 "hubinit - Initialize USB hub\n",
630 NULL
631 );
632 #endif /* CONFIG_I2C_MULTI_BUS */
633
634 #define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
635 int boot_eeprom_write (unsigned dev_addr,
636 unsigned offset,
637 uchar *buffer,
638 unsigned cnt)
639 {
640 unsigned end = offset + cnt;
641 unsigned blk_off;
642 int rcode = 0;
643
644 #if defined(CFG_EEPROM_WREN)
645 eeprom_write_enable(dev_addr, 1);
646 #endif
647 /*
648 * Write data until done or would cross a write page boundary.
649 * We must write the address again when changing pages
650 * because the address counter only increments within a page.
651 */
652
653 while (offset < end) {
654 unsigned alen, len;
655 unsigned maxlen;
656
657 uchar addr[2];
658
659 blk_off = offset & 0xFF; /* block offset */
660
661 addr[0] = offset >> 8; /* block number */
662 addr[1] = blk_off; /* block offset */
663 alen = 2;
664 addr[0] |= dev_addr; /* insert device address */
665
666 len = end - offset;
667
668 /*
669 * For a FRAM device there is no limit on the number of the
670 * bytes that can be ccessed with the single read or write
671 * operation.
672 */
673 #if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
674
675 #define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
676 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
677
678 maxlen = BOOT_EEPROM_PAGE_SIZE -
679 BOOT_EEPROM_PAGE_OFFSET(blk_off);
680 #else
681 maxlen = 0x100 - blk_off;
682 #endif
683 if (maxlen > I2C_RXTX_LEN)
684 maxlen = I2C_RXTX_LEN;
685
686 if (len > maxlen)
687 len = maxlen;
688
689 if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
690 rcode = 1;
691
692 buffer += len;
693 offset += len;
694
695 #if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
696 udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
697 #endif
698 }
699 #if defined(CFG_EEPROM_WREN)
700 eeprom_write_enable(dev_addr, 0);
701 #endif
702 return rcode;
703 }
704
705 int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
706 {
707 ulong sdsdp[4];
708
709 if (argc > 1) {
710 if (!strcmp(argv[1], "533")) {
711 printf("Bootstrapping for 533MHz\n");
712 sdsdp[0] = 0x87788252;
713 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
714 sdsdp[1] = 0x095fa030;
715 sdsdp[2] = 0x40082350;
716 sdsdp[3] = 0x0d050000;
717 } else if (!strcmp(argv[1], "533-66")) {
718 printf("Bootstrapping for 533MHz (66MHz PCI)\n");
719 sdsdp[0] = 0x87788252;
720 /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
721 sdsdp[1] = 0x0957a030;
722 sdsdp[2] = 0x40082350;
723 sdsdp[3] = 0x0d050000;
724 } else if (!strcmp(argv[1], "667")) {
725 printf("Bootstrapping for 667MHz\n");
726 sdsdp[0] = 0x8778a256;
727 /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
728 sdsdp[1] = 0x0947a030;
729 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
730 * -> not working when overclocking 533MHz chips
731 * -> untested on 667MHz chips */
732 /* sdsdp[1]=0x095fa030; */
733 sdsdp[2] = 0x40082350;
734 sdsdp[3] = 0x0d050000;
735 }
736 } else {
737 printf("Bootstrapping for 533MHz (default)\n");
738 sdsdp[0] = 0x87788252;
739 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
740 sdsdp[1] = 0x095fa030;
741 sdsdp[2] = 0x40082350;
742 sdsdp[3] = 0x0d050000;
743 }
744
745 printf("Writing boot EEPROM ...\n");
746 if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
747 0, (uchar*)sdsdp, 16) != 0)
748 printf("boot_eeprom_write failed\n");
749 else
750 printf("done (dump via 'i2c md 52 0.1 10')\n");
751
752 return 0;
753 }
754 U_BOOT_CMD(
755 sbe, 2, 0, do_setup_boot_eeprom,
756 "sbe - setup boot eeprom\n",
757 NULL
758 );
759
760 #if defined(CFG_EEPROM_WREN)
761 /*
762 * Input: <dev_addr> I2C address of EEPROM device to enable.
763 * <state> -1: deliver current state
764 * 0: disable write
765 * 1: enable write
766 * Returns: -1: wrong device address
767 * 0: dis-/en- able done
768 * 0/1: current state if <state> was -1.
769 */
770 int eeprom_write_enable (unsigned dev_addr, int state)
771 {
772 if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
773 (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr))
774 return -1;
775 else {
776 switch (state) {
777 case 1:
778 /* Enable write access, clear bit GPIO_SINT2. */
779 out_be32((void*)GPIO0_OR,
780 in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP);
781 state = 0;
782 break;
783 case 0:
784 /* Disable write access, set bit GPIO_SINT2. */
785 out_be32((void*)GPIO0_OR,
786 in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP);
787 state = 0;
788 break;
789 default:
790 /* Read current status back. */
791 state = (0 == (in_be32((void*)GPIO0_OR) &
792 CFG_GPIO0_EP_EEP));
793 break;
794 }
795 }
796 return state;
797 }
798
799 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
800 {
801 int query = argc == 1;
802 int state = 0;
803
804 if (query) {
805 /* Query write access state. */
806 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
807 if (state < 0)
808 puts ("Query of write access state failed.\n");
809 else {
810 printf ("Write access for device 0x%0x is %sabled.\n",
811 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
812 state = 0;
813 }
814 } else {
815 if ('0' == argv[1][0]) {
816 /* Disable write access. */
817 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
818 } else {
819 /* Enable write access. */
820 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
821 }
822 if (state < 0)
823 puts ("Setup of write access state failed.\n");
824 }
825
826 return state;
827 }
828
829 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
830 "eepwren - Enable / disable / query EEPROM write access\n",
831 NULL);
832 #endif /* #if defined(CFG_EEPROM_WREN) */
833
834 static int got_pldirq;
835
836 static int pld_interrupt(u32 arg)
837 {
838 int rc = -1; /* not for us */
839 u8 status = in8(CFG_CPLD_BASE);
840
841 /* check for PLD interrupt */
842 if (status & PWR_INT_FLAG) {
843 /* reset this int */
844 out8(CFG_CPLD_BASE, 0);
845 rc = 0;
846 got_pldirq = 1; /* trigger backend */
847 }
848
849 return rc;
850 }
851
852 int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
853 {
854 got_pldirq = 0;
855
856 /* clear any pending interrupt */
857 out8(CFG_CPLD_BASE, 0);
858
859 irq_install_handler(CPLD_IRQ,
860 (interrupt_handler_t *)pld_interrupt, 0);
861
862 printf("Waiting ...\n");
863 while(!got_pldirq) {
864 /* Abort if ctrl-c was pressed */
865 if (ctrlc()) {
866 puts("\nAbort\n");
867 break;
868 }
869 }
870 if (got_pldirq) {
871 printf("Got interrupt!\n");
872 printf("Power %sready!\n",
873 in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT ");
874 }
875
876 irq_free_handler(CPLD_IRQ);
877 return 0;
878 }
879 U_BOOT_CMD(
880 wpi, 1, 1, do_waitpwrirq,
881 "wpi - Wait for power change interrupt\n",
882 NULL
883 );
884
885 /*
886 * initialize DVI panellink transmitter
887 */
888 int dvi_init(void)
889 {
890 int i;
891 int ret = 0;
892 unsigned int oldbus;
893 uchar u[] = {0x08, 0x34,
894 0x09, 0x20,
895 0x0a, 0x90,
896 0x0c, 0x89,
897 0x08, 0x35};
898
899 printf("DVI: ");
900
901 oldbus = I2C_GET_BUS();
902 I2C_SET_BUS(0);
903
904 for (i = 0; i < sizeof(u); i += 2)
905 if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
906 ret = -1;
907 break;
908 }
909
910 if (ret == 0)
911 printf("initialized\n");
912 else
913 printf("failed - cannot initialize DVI transmitter\n");
914
915 I2C_SET_BUS(oldbus);
916 return ret;
917 }
918
919 int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
920 {
921 dvi_init();
922 return 0;
923 }
924 U_BOOT_CMD(
925 dviinit, 1, 1, do_dviinit,
926 "dviinit - Initialize DVI Panellink transmitter\n",
927 NULL
928 );
929
930 /*
931 * TODO: 'time' command might be useful for others as well.
932 * Move to 'common' directory.
933 */
934 int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
935 {
936 unsigned long long start, end;
937 char c, cmd[CFG_CBSIZE];
938 char *p, *d = cmd;
939 int ret, i;
940 ulong us;
941
942 for (i = 1; i < argc; i++) {
943 p = argv[i];
944
945 if (i > 1)
946 *d++ = ' ';
947
948 while ((c = *p++) != '\0') {
949 *d++ = c;
950 }
951 }
952 *d = '\0';
953
954 start = get_ticks();
955 ret = run_command (cmd, 0);
956 end = get_ticks();
957
958 printf("ticks=%d\n", (ulong)(end - start));
959 us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
960 printf("usec=%d\n", us);
961
962 return ret;
963 }
964 U_BOOT_CMD(
965 time, CFG_MAXARGS, 1, do_time,
966 "time - run command and output execution time\n",
967 NULL
968 );
969
970 extern void video_hw_rectfill (
971 unsigned int bpp, /* bytes per pixel */
972 unsigned int dst_x, /* dest pos x */
973 unsigned int dst_y, /* dest pos y */
974 unsigned int dim_x, /* frame width */
975 unsigned int dim_y, /* frame height */
976 unsigned int color /* fill color */
977 );
978
979 /*
980 * graphics demo
981 * draw rectangles using pseudorandom number generator
982 * (see http://www.embedded.com/columns/technicalinsights/20900500)
983 */
984 unsigned int rprime = 9972;
985 static unsigned int r;
986 static unsigned int Y;
987
988 unsigned int prng(unsigned int max)
989 {
990 if (r == 0 || r == 1 || r == -1)
991 r = rprime; /* keep from getting stuck */
992
993 r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
994 Y = (r >> 16) % max; /* choose upper bits and reduce */
995 return Y;
996 }
997
998 int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
999 {
1000 unsigned int color;
1001 unsigned int x, y, dx, dy;
1002
1003 while (!ctrlc()) {
1004 x = prng(1280 - 1);
1005 y = prng(1024 - 1);
1006 dx = prng(1280- x - 1);
1007 dy = prng(1024 - y - 1);
1008 color = prng(0x10000);
1009 video_hw_rectfill(2, x, y, dx, dy, color);
1010 }
1011
1012 return 0;
1013 }
1014 U_BOOT_CMD(
1015 gfxdemo, CFG_MAXARGS, 1, do_gfxdemo,
1016 "gfxdemo - demo\n",
1017 NULL
1018 );
"Das U-Boot" Source Tree