2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2009 Stefan Roese <sr@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/bitops.h>
13 #include <asm/processor.h>
14 #include <asm/mpc512x.h>
15 #include <fdt_support.h>
17 DECLARE_GLOBAL_DATA_PTR
;
19 int eeprom_write_enable(unsigned dev_addr
, int state
)
24 int board_early_init_f(void)
26 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
30 * Initialize Local Window for boot access
32 out_be32(&im
->sysconf
.lpbaw
,
33 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
34 sync_law(&im
->sysconf
.lpbaw
);
37 * Configure MSCAN clocks
40 out_be32(&im
->clk
.msccr
[i
], 0x00300000);
41 out_be32(&im
->clk
.msccr
[i
], 0x00310000);
47 clrbits_be32(&im
->gpio
.gpodr
, 0x000000e0);
48 clrbits_be32(&im
->gpio
.gpdir
, 0x00ef0000);
49 setbits_be32(&im
->gpio
.gpdir
, 0x001000e0);
50 setbits_be32(&im
->gpio
.gpdat
, 0x00100000);
57 gd
->ram_size
= get_ram_size(0, fixed_sdram(NULL
, NULL
, 0));
64 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
68 * Optimize access to profibus chip (VPC3) on the local bus
72 * Select 1:1 for LPC_DIV
74 val
= in_be32(&im
->clk
.scfr
[0]) & ~SCFR1_LPC_DIV_MASK
;
75 out_be32(&im
->clk
.scfr
[0], val
| (0x1 << SCFR1_LPC_DIV_SHIFT
));
78 * Configure LPC Chips Select Deadcycle Control Register
79 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
80 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
82 clrbits_be32(&im
->lpc
.cs_dccr
, 0x000000ff);
83 setbits_be32(&im
->lpc
.cs_dccr
, (0x00 << 4) | (0x01 << 0));
86 * Configure LPC Chips Select Holdcycle Control Register
87 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
88 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
90 clrbits_be32(&im
->lpc
.cs_hccr
, 0x000000ff);
91 setbits_be32(&im
->lpc
.cs_hccr
, (0x00 << 4) | (0x01 << 0));
96 static iopin_t ioregs_init
[] = {
97 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
99 offsetof(struct ioctrl512x
, io_control_spdif_txclk
), 3, 0,
100 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
101 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
103 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
105 offsetof(struct ioctrl512x
, io_control_psc0_0
), 15, 0,
106 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
107 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
109 /* FUNC1=SELECT LPC_CS1 */
111 offsetof(struct ioctrl512x
, io_control_lpc_cs1
), 1, 0,
112 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
113 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
115 /* FUNC3=SELECT PSC5_2 */
117 offsetof(struct ioctrl512x
, io_control_psc5_2
), 1, 0,
118 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
119 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
121 /* FUNC3=SELECT PSC5_3 */
123 offsetof(struct ioctrl512x
, io_control_psc5_3
), 1, 0,
124 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
125 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
127 /* FUNC3=SELECT PSC7_3 */
129 offsetof(struct ioctrl512x
, io_control_psc7_3
), 1, 0,
130 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
131 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
133 /* FUNC3=SELECT PSC9_0 */
135 offsetof(struct ioctrl512x
, io_control_psc9_0
), 3, 0,
136 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
137 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
139 /* FUNC3=SELECT PSC10_0 */
141 offsetof(struct ioctrl512x
, io_control_psc10_0
), 3, 0,
142 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
143 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
145 /* FUNC3=SELECT PSC10_3 */
147 offsetof(struct ioctrl512x
, io_control_psc10_3
), 1, 0,
148 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
149 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
151 /* FUNC3=SELECT PSC11_0 */
153 offsetof(struct ioctrl512x
, io_control_psc11_0
), 4, 0,
154 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
155 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
157 /* FUNC0=SELECT IRQ0 */
159 offsetof(struct ioctrl512x
, io_control_irq0
), 4, 0,
160 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
161 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
165 static iopin_t rev2_silicon_pci_ioregs_init
[] = {
166 /* FUNC0=PCI Sets next 54 to PCI pads */
168 offsetof(struct ioctrl512x
, io_control_pci_ad31
), 54, 0,
169 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
175 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
178 puts("Board: MECP_5123\n");
181 * Initialize function mux & slew rate IO inter alia on IO
184 iopin_initialize(ioregs_init
, ARRAY_SIZE(ioregs_init
));
186 spridr
= in_be32(&im
->sysconf
.spridr
);
187 if (SVR_MJREV(spridr
) >= 2)
188 iopin_initialize(rev2_silicon_pci_ioregs_init
, 1);
193 #ifdef CONFIG_OF_BOARD_SETUP
194 int ft_board_setup(void *blob
, bd_t
*bd
)
196 ft_cpu_setup(blob
, bd
);
200 #endif /* CONFIG_OF_BOARD_SETUP */