board/esd/meesc/meesc.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2009-2011
   7  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   8  * esd electronic system design gmbh <www.esd.eu>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <asm/io.h>
  31 #include <asm/arch/at91sam9_smc.h>
  32 #include <asm/arch/at91_common.h>
  33 #include <asm/arch/at91_pmc.h>
  34 #include <asm/arch/at91_rstc.h>
  35 #include <asm/arch/at91_matrix.h>
  36 #include <asm/arch/at91_pio.h>
  37 #include <asm/arch/clk.h>
  38 #include <netdev.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /*
  43  * Miscelaneous platform dependent initialisations
  44  */
  45
  46 static int hw_rev = -1; /* hardware revision */
  47
  48 int get_hw_rev(void)
  49 {
  50         if (hw_rev >= 0)
  51                 return hw_rev;
  52
  53         hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
  54         hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
  55         hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
  56         hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
  57
  58         if (hw_rev == 15)
  59                 hw_rev = 0;
  60
  61         return hw_rev;
  62 }
  63
  64 #ifdef CONFIG_CMD_NAND
  65 static void meesc_nand_hw_init(void)
  66 {
  67         unsigned long csa;
  68         at91_smc_t      *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  69         at91_matrix_t   *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  70
  71         /* Enable CS3 */
  72         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  73         writel(csa, &matrix->csa[0]);
  74
  75         /* Configure SMC CS3 for NAND/SmartMedia */
  76         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  77                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  78                 &smc->cs[3].setup);
  79
  80         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  81                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  82                 &smc->cs[3].pulse);
  83
  84         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  85                 &smc->cs[3].cycle);
  86         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  87                 AT91_SMC_MODE_EXNW_DISABLE |
  88                 AT91_SMC_MODE_DBW_8 |
  89                 AT91_SMC_MODE_TDF_CYCLE(3),
  90                 &smc->cs[3].mode);
  91
  92         /* Configure RDY/BSY */
  93         at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  94
  95         /* Enable NandFlash */
  96         at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  97 }
  98 #endif /* CONFIG_CMD_NAND */
  99
 100 #ifdef CONFIG_MACB
 101 static void meesc_macb_hw_init(void)
 102 {
 103         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 104         /* Enable clock */
 105         writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 106         at91_macb_hw_init();
 107 }
 108 #endif
 109
 110 /*
 111  * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
 112  * controller debugging
 113  * The ET1100 is located at physical address 0x70000000
 114  * Its process memory is located at physical address 0x70001000
 115  */
 116 static void meesc_ethercat_hw_init(void)
 117 {
 118         at91_smc_t      *smc1   = (at91_smc_t *) ATMEL_BASE_SMC1;
 119
 120         /* Configure SMC EBI1_CS0 for EtherCAT */
 121         writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
 122                 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
 123                 &smc1->cs[0].setup);
 124         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
 125                 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
 126                 &smc1->cs[0].pulse);
 127         writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
 128                 &smc1->cs[0].cycle);
 129         /*
 130          * Configure behavior at external wait signal, byte-select mode, 16 bit
 131          * data bus width, none data float wait states and TDF optimization
 132          */
 133         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
 134                 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
 135                 AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
 136
 137         /* Configure RDY/BSY */
 138         at91_set_b_periph(AT91_PIO_PORTE, 20, 0);       /* EBI1_NWAIT */
 139 }
 140
 141 int dram_init(void)
 142 {
 143         gd->ram_size = get_ram_size(
 144                 (void *)CONFIG_SYS_SDRAM_BASE,
 145                 CONFIG_SYS_SDRAM_SIZE);
 146         return 0;
 147 }
 148
 149 int board_eth_init(bd_t *bis)
 150 {
 151         int rc = 0;
 152 #ifdef CONFIG_MACB
 153         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 154 #endif
 155         return rc;
 156 }
 157
 158 int checkboard(void)
 159 {
 160         char str[32];
 161         u_char hw_type; /* hardware type */
 162
 163         /* read the "Type" register of the ET1100 controller */
 164         hw_type = readb(CONFIG_ET1100_BASE);
 165
 166         switch (hw_type) {
 167         case 0x11:
 168         case 0x3F:
 169                 /* ET1100 present, arch number of MEESC-Board */
 170                 gd->bd->bi_arch_number = MACH_TYPE_MEESC;
 171                 puts("Board: CAN-EtherCAT Gateway");
 172                 break;
 173         case 0xFF:
 174                 /* no ET1100 present, arch number of EtherCAN/2-Board */
 175                 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
 176                 puts("Board: EtherCAN/2 Gateway");
 177                 /* switch on LED1D */
 178                 at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
 179                 break;
 180         default:
 181                 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
 182                 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
 183                 printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
 184                 puts("Board: EtherCAN/2 Gateway");
 185                 break;
 186         }
 187         if (getenv_f("serial#", str, sizeof(str)) > 0) {
 188                 puts(", serial# ");
 189                 puts(str);
 190         }
 191         printf("\nHardware-revision: 1.%d\n", get_hw_rev());
 192         printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
 193         return 0;
 194 }
 195
 196 #ifdef CONFIG_SERIAL_TAG
 197 void get_board_serial(struct tag_serialnr *serialnr)
 198 {
 199         char *str;
 200
 201         char *serial = getenv("serial#");
 202         if (serial) {
 203                 str = strchr(serial, '_');
 204                 if (str && (strlen(str) >= 4)) {
 205                         serialnr->high = (*(str + 1) << 8) | *(str + 2);
 206                         serialnr->low = simple_strtoul(str + 3, NULL, 16);
 207                 }
 208         } else {
 209                 serialnr->high = 0;
 210                 serialnr->low = 0;
 211         }
 212 }
 213 #endif
 214
 215 #ifdef CONFIG_REVISION_TAG
 216 u32 get_board_rev(void)
 217 {
 218         return hw_rev | 0x100;
 219 }
 220 #endif
 221
 222 #ifdef CONFIG_MISC_INIT_R
 223 int misc_init_r(void)
 224 {
 225         char            *str;
 226         char            buf[32];
 227         at91_pmc_t      *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 228
 229         /*
 230          * Normally the processor clock has a divisor of 2.
 231          * In some cases this this needs to be set to 4.
 232          * Check the user has set environment mdiv to 4 to change the divisor.
 233          */
 234         if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
 235                 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
 236                         AT91SAM9_PMC_MDIV_4, &pmc->mckr);
 237                 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
 238                 serial_setbrg();
 239                 /* Notify the user that the clock is not default */
 240                 printf("Setting master clock to %s MHz\n",
 241                         strmhz(buf, get_mck_clk_rate()));
 242         }
 243
 244         return 0;
 245 }
 246 #endif /* CONFIG_MISC_INIT_R */
 247
 248 int board_early_init_f(void)
 249 {
 250         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 251
 252         /* enable all clocks */
 253         writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 254                 (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP),
 255                 &pmc->pcer);
 256
 257         at91_seriald_hw_init();
 258
 259         return 0;
 260 }
 261
 262 int board_init(void)
 263 {
 264         /* initialize ET1100 Controller */
 265         meesc_ethercat_hw_init();
 266
 267         /* adress of boot parameters */
 268         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 269
 270 #ifdef CONFIG_CMD_NAND
 271         meesc_nand_hw_init();
 272 #endif
 273 #ifdef CONFIG_HAS_DATAFLASH
 274         at91_spi0_hw_init(1 << 0);
 275 #endif
 276 #ifdef CONFIG_MACB
 277         meesc_macb_hw_init();
 278 #endif
 279 #ifdef CONFIG_AT91_CAN
 280         at91_can_hw_init();
 281 #endif
 282 #ifdef CONFIG_USB_OHCI_NEW
 283         at91_uhp_hw_init();
 284 #endif
 285         return 0;
 286 }