3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <fdt_support.h>
12 #include <asm/processor.h>
14 #include <asm/ppc4xx-gpio.h>
15 #include <asm/4xx_pci.h>
20 * PMC405-DE cpld registers
21 * - all registers are 8 bit
22 * - all registers are on 32 bit addesses
24 struct pmc405de_cpld
{
25 /* cpld design version */
29 /* misc. status lines */
35 * gate bit(s) must be written with '1' to
42 #define CPLD_VERSION_MASK 0x0f
43 #define CPLD_CONTROL_POSTLED_N 0x01
44 #define CPLD_CONTROL_POSTLED_GATE 0x02
45 #define CPLD_CONTROL_RESETOUT_N 0x40
46 #define CPLD_CONTROL_RESETOUT_N_GATE 0x80
48 DECLARE_GLOBAL_DATA_PTR
;
50 extern void __ft_board_setup(void *blob
, bd_t
*bd
);
51 extern void pll_write(u32 a
, u32 b
);
53 static int wait_for_pci_ready_done
;
55 static int is_monarch(void);
56 static int pci_is_66mhz(void);
57 static int board_revision(void);
58 static int cpld_revision(void);
59 static void upd_plb_pci_div(u32 pllmr0
, u32 pllmr1
, u32 div
);
61 int board_early_init_f(void)
66 * check M66EN and patch PLB:PCI divider for 66MHz PCI
68 * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
69 * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
70 * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
71 * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
73 * calling upd_plb_pci_div() may end in calling pll_write() which will
74 * do a chip reset and never return.
76 pllmr0
= mfdcr(CPC0_PLLMR0
);
77 pllmr1
= mfdcr(CPC0_PLLMR1
);
79 if ((pllmr0
& PLLMR0_CPU_TO_PLB_MASK
) == PLLMR0_CPU_PLB_DIV_3
) {
80 /* fCPU=333MHz, fPLB=111MHz */
82 upd_plb_pci_div(pllmr0
, pllmr1
, PLLMR0_PCI_PLB_DIV_1
);
84 upd_plb_pci_div(pllmr0
, pllmr1
, PLLMR0_PCI_PLB_DIV_2
);
86 /* fCPU=133|266MHz, fPLB=133MHz */
88 upd_plb_pci_div(pllmr0
, pllmr1
, PLLMR0_PCI_PLB_DIV_2
);
90 upd_plb_pci_div(pllmr0
, pllmr1
, PLLMR0_PCI_PLB_DIV_3
);
94 * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
95 * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
96 * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
97 * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
98 * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
99 * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
100 * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
102 mtdcr(UIC0SR
, 0xFFFFFFFF); /* clear all ints */
103 mtdcr(UIC0ER
, 0x00000000); /* disable all ints */
104 mtdcr(UIC0CR
, 0x00000000); /* set all to be non-critical*/
105 mtdcr(UIC0PR
, 0xFFFFFF80); /* set int polarities */
106 mtdcr(UIC0TR
, 0x10000000); /* set int trigger levels */
107 mtdcr(UIC0VCR
, 0x00000001); /* set vect base=0, INT0 highest prio */
108 mtdcr(UIC0SR
, 0xFFFFFFFF); /* clear all ints */
111 * EBC Configuration Register:
112 * - set ready timeout to 512 ebc-clks -> ca. 15 us
113 * - EBC lines are always driven
115 mtebc(EBC0_CFG
, 0xa8400000);
120 static void upd_plb_pci_div(u32 pllmr0
, u32 pllmr1
, u32 div
)
122 if ((pllmr0
& PLLMR0_PCI_TO_PLB_MASK
) != div
)
123 pll_write((pllmr0
& ~PLLMR0_PCI_TO_PLB_MASK
) | div
, pllmr1
);
126 int misc_init_r(void)
129 struct ppc4xx_gpio
*gpio0
= (struct ppc4xx_gpio
*)GPIO_BASE
;
130 struct pmc405de_cpld
*cpld
=
131 (struct pmc405de_cpld
*)CONFIG_SYS_CPLD_BASE
;
134 /* PCI configuration done: release EREADY */
135 setbits_be32(&gpio0
->or, CONFIG_SYS_GPIO_EREADY
);
136 setbits_be32(&gpio0
->tcr
, CONFIG_SYS_GPIO_EREADY
);
139 /* turn off POST LED */
140 out_8(&cpld
->control
,
141 CPLD_CONTROL_POSTLED_N
| CPLD_CONTROL_POSTLED_GATE
);
143 /* turn on LEDs: RUN, A, B */
144 clrbits_be32(&gpio0
->or,
145 CONFIG_SYS_GPIO_LEDRUN_N
|
146 CONFIG_SYS_GPIO_LEDA_N
|
147 CONFIG_SYS_GPIO_LEDB_N
);
149 for (i
=0; i
< 200; i
++)
152 /* turn off LEDs: A, B */
153 setbits_be32(&gpio0
->or,
154 CONFIG_SYS_GPIO_LEDA_N
|
155 CONFIG_SYS_GPIO_LEDB_N
);
160 static int is_monarch(void)
162 struct ppc4xx_gpio
*gpio0
= (struct ppc4xx_gpio
*)GPIO_BASE
;
163 return (in_be32(&gpio0
->ir
) & CONFIG_SYS_GPIO_MONARCH_N
) == 0;
166 static int pci_is_66mhz(void)
168 struct ppc4xx_gpio
*gpio0
= (struct ppc4xx_gpio
*)GPIO_BASE
;
169 return (in_be32(&gpio0
->ir
) & CONFIG_SYS_GPIO_M66EN
);
172 static int board_revision(void)
174 struct ppc4xx_gpio
*gpio0
= (struct ppc4xx_gpio
*)GPIO_BASE
;
175 return ((in_be32(&gpio0
->ir
) & CONFIG_SYS_GPIO_HWREV_MASK
) >>
176 CONFIG_SYS_GPIO_HWREV_SHIFT
);
179 static int cpld_revision(void)
181 struct pmc405de_cpld
*cpld
=
182 (struct pmc405de_cpld
*)CONFIG_SYS_CPLD_BASE
;
183 return ((in_8(&cpld
->version
) & CPLD_VERSION_MASK
));
187 * Check Board Identity
191 puts("Board: esd GmbH - PMC-CPU/405-DE");
193 gd
->board_type
= board_revision();
194 printf(", Rev 1.%ld, ", gd
->board_type
);
199 printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
200 pci_is_66mhz() ? "66" : "33", cpld_revision());
206 static void wait_for_pci_ready(void)
208 struct ppc4xx_gpio
*gpio0
= (struct ppc4xx_gpio
*)GPIO_BASE
;
210 char *s
= getenv("pcidelay");
213 if (wait_for_pci_ready_done
)
217 * We have our own handling of the pcidelay variable.
218 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
219 * and adapter devices. For adapter devices we do not
223 int ms
= simple_strtoul(s
, NULL
, 10);
224 printf("PCI: Waiting for %d ms\n", ms
);
229 if (!(in_be32(&gpio0
->ir
) & CONFIG_SYS_GPIO_EREADY
)) {
230 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
236 if (in_be32(&gpio0
->ir
) & CONFIG_SYS_GPIO_EREADY
) {
243 wait_for_pci_ready_done
= 1;
247 * Overwrite weak is_pci_host()
249 * This routine is called to determine if a pci scan should be
250 * performed. With various hardware environments (especially cPCI and
251 * PPMC) it's insufficient to depend on the state of the arbiter enable
252 * bit in the strap register, or generic host/adapter assumptions.
254 * Return 0 for adapter mode, non-zero for host (monarch) mode.
256 int is_pci_host(struct pci_controller
*hose
)
262 * Overwrite PCI identification when running in
264 * This should be moved into pci_target_init()
265 * when it is sometimes available for 405 CPUs
267 pci_write_config_word(PCIDEVID_405GP
,
269 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH
);
270 pci_write_config_word(PCIDEVID_405GP
,
272 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH
);
275 s
= getenv("pciscan");
278 wait_for_pci_ready();
284 if (!strcmp(s
, "yes"))
292 * Overwrite weak pci_pre_init()
294 * The default implementation enables the 405EP
295 * internal PCI arbiter. We do not want that
298 int pci_pre_init(struct pci_controller
*hose
)
303 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
304 int ft_board_setup(void *blob
, bd_t
*bd
)
308 __ft_board_setup(blob
, bd
);
311 * Disable PCI in non-monarch mode.
314 rc
= fdt_find_and_setprop(blob
, "/plb/pci@ec000000", "status",
315 "disabled", sizeof("disabled"), 1);
317 printf("Unable to update property status in PCI node, "
325 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
327 #if defined(CONFIG_SYS_EEPROM_WREN)
328 /* Input: <dev_addr> I2C address of EEPROM device to enable.
329 * <state> -1: deliver current state
332 * Returns: -1: wrong device address
333 * 0: dis-/en- able done
334 * 0/1: current state if <state> was -1.
336 int eeprom_write_enable(unsigned dev_addr
, int state
)
338 struct ppc4xx_gpio
*gpio0
= (struct ppc4xx_gpio
*)GPIO_BASE
;
340 if (CONFIG_SYS_I2C_EEPROM_ADDR
!= dev_addr
) {
345 /* Enable write access, clear bit GPIO0. */
346 clrbits_be32(&gpio0
->or, CONFIG_SYS_GPIO_EEPROM_WP
);
350 /* Disable write access, set bit GPIO0. */
351 setbits_be32(&gpio0
->or, CONFIG_SYS_GPIO_EEPROM_WP
);
355 /* Read current status back. */
356 state
= (0 == (in_be32(&gpio0
->or) &
357 CONFIG_SYS_GPIO_EEPROM_WP
));
364 int do_eep_wren(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
366 int query
= argc
== 1;
370 /* Query write access state. */
371 state
= eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR
, - 1);
373 puts("Query of write access state failed.\n");
375 printf("Write access for device 0x%0x is %sabled.\n",
376 CONFIG_SYS_I2C_EEPROM_ADDR
,
377 state
? "en" : "dis");
381 if ('0' == argv
[1][0]) {
382 /* Disable write access. */
383 state
= eeprom_write_enable(
384 CONFIG_SYS_I2C_EEPROM_ADDR
, 0);
386 /* Enable write access. */
387 state
= eeprom_write_enable(
388 CONFIG_SYS_I2C_EEPROM_ADDR
, 1);
391 puts ("Setup of write access state failed.\n");
397 U_BOOT_CMD(eepwren
, 2, 0, do_eep_wren
,
398 "Enable / disable / query EEPROM write access",
401 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
403 #if defined(CONFIG_PRAM)
404 #include <environment.h>
406 int do_painit(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
408 u32 pram
, nextbase
, base
;
415 pram
= simple_strtoul(v
, NULL
, 10);
417 printf("Error: pram undefined. Please define pram in KiB\n");
421 base
= gd
->bd
->bi_memsize
;
422 #if defined(CONFIG_LOGBUFFER)
423 base
-= LOGBUFF_LEN
+ LOGBUFF_OVERHEAD
;
426 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
428 param
= base
- (pram
<< 10);
429 printf("PARAM: @%08x\n", param
);
430 debug("memsize=0x%08x, base=0x%08x\n", (u32
)gd
->bd
->bi_memsize
, base
);
432 /* clear entire PA ram */
433 memset((void*)param
, 0, (pram
<< 10));
435 /* reserve 4k for pointer field */
436 nextbase
= base
- 4096;
437 lptr
= (ulong
*)(base
);
440 * *(--lptr) = item_size;
441 * *(--lptr) = base - item_base = distance from field top;
444 /* env is first (4k aligned) */
445 nextbase
-= ((CONFIG_ENV_SIZE
+ 4096 - 1) & ~(4096 - 1));
446 memcpy((void*)nextbase
, env_ptr
, CONFIG_ENV_SIZE
);
447 *(--lptr
) = CONFIG_ENV_SIZE
; /* size */
448 *(--lptr
) = base
- nextbase
; /* offset | type=0 */
451 *(--lptr
) = nextbase
- param
; /* size */
452 *(--lptr
) = (base
- param
) | 126; /* offset | type=126 */
454 /* terminate pointer field */
455 *(--lptr
) = crc32(0, (void*)(base
- 0x10), 0x10);
456 *(--lptr
) = 0; /* offset=0 -> terminator */
460 painit
, 1, 1, do_painit
,
461 "prepare PciAccess system",
464 #endif /* CONFIG_PRAM */
466 int do_selfreset(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
468 struct ppc4xx_gpio
*gpio0
= (struct ppc4xx_gpio
*)GPIO_BASE
;
469 setbits_be32(&gpio0
->tcr
, CONFIG_SYS_GPIO_SELFRST_N
);
473 selfreset
, 1, 1, do_selfreset
,
474 "assert self-reset# signal",
478 int do_resetout(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
480 struct pmc405de_cpld
*cpld
=
481 (struct pmc405de_cpld
*)CONFIG_SYS_CPLD_BASE
;
484 if (argv
[1][0] == '0') {
486 printf("PMC-RESETOUT# asserted\n");
487 out_8(&cpld
->control
,
488 CPLD_CONTROL_RESETOUT_N_GATE
);
491 printf("PMC-RESETOUT# deasserted\n");
492 out_8(&cpld
->control
,
493 CPLD_CONTROL_RESETOUT_N
|
494 CPLD_CONTROL_RESETOUT_N_GATE
);
497 printf("PMC-RESETOUT# is %s\n",
498 (in_8(&cpld
->control
) & CPLD_CONTROL_RESETOUT_N
) ?
499 "inactive" : "active");
504 resetout
, 2, 1, do_resetout
,
505 "assert PMC-RESETOUT# signal",