2 * (C) Copyright 2007-2008
3 * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/cache.h>
11 #include <asm/processor.h>
12 #if defined(CONFIG_LOGBUFFER)
19 int bootstrap_eeprom_write(unsigned dev_addr
, unsigned offset
,
20 uchar
*buffer
, unsigned cnt
);
21 int eeprom_write_enable(unsigned dev_addr
, int state
);
23 DECLARE_GLOBAL_DATA_PTR
;
25 #if defined(CONFIG_CMD_BSP)
27 static int got_fifoirq
;
30 int fpga_interrupt(u32 arg
)
32 pmc440_fpga_t
*fpga
= (pmc440_fpga_t
*)arg
;
33 int rc
= -1; /* not for us */
34 u32 status
= FPGA_IN32(&fpga
->status
);
36 /* check for interrupt from fifo module */
37 if (status
& STATUS_FIFO_ISF
) {
38 /* disable this int source */
39 FPGA_OUT32(&fpga
->hostctrl
, HOSTCTRL_FIFOIE_GATE
);
41 got_fifoirq
= 1; /* trigger backend */
44 if (status
& STATUS_HOST_ISF
) {
45 FPGA_OUT32(&fpga
->hostctrl
, HOSTCTRL_HCINT_GATE
);
53 int do_waithci(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
55 pmc440_fpga_t
*fpga
= (pmc440_fpga_t
*)FPGA_BA
;
59 FPGA_CLRBITS(&fpga
->ctrla
, CTRL_HOST_IE
);
60 FPGA_OUT32(&fpga
->hostctrl
, HOSTCTRL_HCINT_GATE
);
62 irq_install_handler(IRQ0_FPGA
,
63 (interrupt_handler_t
*)fpga_interrupt
,
66 FPGA_SETBITS(&fpga
->ctrla
, CTRL_HOST_IE
);
69 /* Abort if ctrl-c was pressed */
76 printf("Got interrupt!\n");
78 FPGA_CLRBITS(&fpga
->ctrla
, CTRL_HOST_IE
);
79 irq_free_handler(IRQ0_FPGA
);
83 waithci
, 1, 1, do_waithci
,
84 "Wait for host control interrupt",
88 void dump_fifo(pmc440_fpga_t
*fpga
, int f
, int *n
)
92 while (!((ctrl
= FPGA_IN32(&fpga
->fifo
[f
].ctrl
)) & FIFO_EMPTY
)) {
93 printf("%5d %d %3d %08x",
94 (*n
)++, f
, ctrl
& (FIFO_LEVEL_MASK
| FIFO_FULL
),
95 FPGA_IN32(&fpga
->fifo
[f
].data
));
96 if (ctrl
& FIFO_OVERFLOW
) {
97 printf(" OVERFLOW\n");
98 FPGA_CLRBITS(&fpga
->fifo
[f
].ctrl
, FIFO_OVERFLOW
);
104 int do_fifo(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
106 pmc440_fpga_t
*fpga
= (pmc440_fpga_t
*)FPGA_BA
;
110 char str
[] = "\\|/-";
117 /* print all fifos status information */
118 printf("fifo level status\n");
119 printf("______________________________\n");
120 for (i
=0; i
<FIFO_COUNT
; i
++) {
121 ctrl
= FPGA_IN32(&fpga
->fifo
[i
].ctrl
);
122 printf(" %d %3d %s%s%s %s\n",
123 i
, ctrl
& (FIFO_LEVEL_MASK
| FIFO_FULL
),
124 ctrl
& FIFO_FULL
? "FULL " : "",
125 ctrl
& FIFO_EMPTY
? "EMPTY " : "",
126 ctrl
& (FIFO_FULL
|FIFO_EMPTY
) ? "" : "NOT EMPTY",
127 ctrl
& FIFO_OVERFLOW
? "OVERFLOW" : "");
132 /* completely read out fifo 'n' */
133 if (!strcmp(argv
[1],"read")) {
134 printf(" # fifo level data\n");
135 printf("______________________________\n");
137 for (i
=0; i
<FIFO_COUNT
; i
++)
138 dump_fifo(fpga
, i
, &n
);
140 } else if (!strcmp(argv
[1],"wait")) {
143 irq_install_handler(IRQ0_FPGA
,
144 (interrupt_handler_t
*)fpga_interrupt
,
147 printf(" # fifo level data\n");
148 printf("______________________________\n");
150 /* enable all fifo interrupts */
151 FPGA_OUT32(&fpga
->hostctrl
,
152 HOSTCTRL_FIFOIE_GATE
| HOSTCTRL_FIFOIE_FLAG
);
153 for (i
=0; i
<FIFO_COUNT
; i
++) {
154 /* enable interrupts from all fifos */
155 FPGA_SETBITS(&fpga
->fifo
[i
].ctrl
, FIFO_IE
);
160 while (!got_fifoirq
) {
162 if (!(count
% 100)) {
164 putc(0x08); /* backspace */
165 putc(str
[count2
% 4]);
168 /* Abort if ctrl-c was pressed */
169 if ((abort
= ctrlc())) {
178 /* simple fifo backend */
180 for (i
=0; i
<FIFO_COUNT
; i
++)
181 dump_fifo(fpga
, i
, &n
);
184 /* unmask global fifo irq */
185 FPGA_OUT32(&fpga
->hostctrl
,
186 HOSTCTRL_FIFOIE_GATE
|
187 HOSTCTRL_FIFOIE_FLAG
);
191 /* disable all fifo interrupts */
192 FPGA_OUT32(&fpga
->hostctrl
, HOSTCTRL_FIFOIE_GATE
);
193 for (i
=0; i
<FIFO_COUNT
; i
++)
194 FPGA_CLRBITS(&fpga
->fifo
[i
].ctrl
, FIFO_IE
);
196 irq_free_handler(IRQ0_FPGA
);
199 printf("Usage:\nfifo %s\n", cmdtp
->help
);
206 if (!strcmp(argv
[1],"write")) {
207 /* get fifo number or fifo address */
208 f
= simple_strtoul(argv
[2], NULL
, 16);
211 data
= simple_strtoul(argv
[3], NULL
, 16);
213 /* get optional count parameter */
216 n
= (int)simple_strtoul(argv
[4], NULL
, 10);
218 if (f
< FIFO_COUNT
) {
219 printf("writing %d x %08x to fifo %d\n",
222 FPGA_OUT32(&fpga
->fifo
[f
].data
, data
);
224 printf("writing %d x %08x to fifo port at "
228 out_be32((void *)f
, data
);
231 printf("Usage:\nfifo %s\n", cmdtp
->help
);
237 printf("Usage:\nfifo %s\n", cmdtp
->help
);
244 "Fifo module operations",
246 "fifo write fifo(0..3) data [cnt=1]\n"
247 "fifo write address(>=4) data [cnt=1]\n"
248 " - without arguments: print all fifo's status\n"
249 " - with 'wait' argument: interrupt driven read from all fifos\n"
250 " - with 'read' argument: read current contents from all fifos\n"
251 " - with 'write' argument: write 'data' 'cnt' times to "
252 "'fifo' or 'address'"
255 int do_setup_bootstrap_eeprom(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
262 printf("Usage:\nsbe %s\n", cmdtp
->help
);
267 if (!strcmp(argv
[1], "400")) {
268 /* PLB=133MHz, PLB/PCI=3 */
269 printf("Bootstrapping for 400MHz\n");
274 } else if (!strcmp(argv
[1], "533")) {
275 /* PLB=133MHz, PLB/PCI=3 */
276 printf("Bootstrapping for 533MHz\n");
281 } else if (!strcmp(argv
[1], "667")) {
282 /* PLB=133MHz, PLB/PCI=3 */
283 printf("Bootstrapping for 667MHz\n");
289 printf("Usage:\nsbe %s\n", cmdtp
->help
);
298 else if (argv
[2][0]=='0')
305 delay
= simple_strtoul(argv
[3], NULL
, 10);
311 printf("Writing boot EEPROM ...\n");
312 if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR
,
313 0, (uchar
*)sdsdp
, count
) != 0)
314 printf("bootstrap_eeprom_write failed\n");
316 printf("done (dump via 'i2c md 52 0.1 14')\n");
321 sbe
, 4, 0, do_setup_bootstrap_eeprom
,
322 "setup bootstrap eeprom",
323 "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
326 #if defined(CONFIG_PRAM)
327 #include <environment.h>
331 int do_painit(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
333 u32 pram
, nextbase
, base
;
344 pram
= simple_strtoul(v
, NULL
, 10);
346 printf("Error: pram undefined. Please define pram in KiB\n");
350 base
= gd
->bd
->bi_memsize
;
351 #if defined(CONFIG_LOGBUFFER)
352 base
-= LOGBUFF_LEN
+ LOGBUFF_OVERHEAD
;
355 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
357 param
= base
- (pram
<< 10);
358 printf("PARAM: @%08x\n", param
);
359 debug("memsize=0x%08x, base=0x%08x\n", (u32
)gd
->bd
->bi_memsize
, base
);
361 /* clear entire PA ram */
362 memset((void*)param
, 0, (pram
<< 10));
364 /* reserve 4k for pointer field */
365 nextbase
= base
- 4096;
366 lptr
= (ulong
*)(base
);
369 * *(--lptr) = item_size;
370 * *(--lptr) = base - item_base = distance from field top;
373 /* env is first (4k aligned) */
374 nextbase
-= ((CONFIG_ENV_SIZE
+ 4096 - 1) & ~(4096 - 1));
375 envp
= (env_t
*)nextbase
;
376 res
= (char *)envp
->data
;
377 len
= hexport_r(&env_htab
, '\0', 0, &res
, ENV_SIZE
, 0, NULL
);
379 error("Cannot export environment: errno = %d\n", errno
);
382 envp
->crc
= crc32(0, envp
->data
, ENV_SIZE
);
384 *(--lptr
) = CONFIG_ENV_SIZE
; /* size */
385 *(--lptr
) = base
- nextbase
; /* offset | type=0 */
388 *(--lptr
) = nextbase
- param
; /* size */
389 *(--lptr
) = (base
- param
) | 126; /* offset | type=126 */
391 /* terminate pointer field */
392 *(--lptr
) = crc32(0, (void*)(base
- 0x10), 0x10);
393 *(--lptr
) = 0; /* offset=0 -> terminator */
397 painit
, 1, 1, do_painit
,
398 "prepare PciAccess system",
401 #endif /* CONFIG_PRAM */
403 int do_selfreset(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
405 in_be32((void*)CONFIG_SYS_RESET_BASE
);
409 selfreset
, 1, 1, do_selfreset
,
410 "assert self-reset# signal",
414 int do_resetout(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
416 pmc440_fpga_t
*fpga
= (pmc440_fpga_t
*)FPGA_BA
;
418 /* requiers bootet FPGA and PLD_IOEN_N active */
419 if (in_be32((void*)GPIO1_OR
) & GPIO1_IOEN_N
) {
420 printf("Error: resetout requires a bootet FPGA\n");
425 if (argv
[1][0] == '0') {
427 printf("PMC-RESETOUT# asserted\n");
428 FPGA_OUT32(&fpga
->hostctrl
,
429 HOSTCTRL_PMCRSTOUT_GATE
);
432 printf("PMC-RESETOUT# deasserted\n");
433 FPGA_OUT32(&fpga
->hostctrl
,
434 HOSTCTRL_PMCRSTOUT_GATE
|
435 HOSTCTRL_PMCRSTOUT_FLAG
);
438 printf("PMC-RESETOUT# is %s\n",
439 FPGA_IN32(&fpga
->hostctrl
) & HOSTCTRL_PMCRSTOUT_FLAG
?
440 "inactive" : "active");
446 resetout
, 2, 1, do_resetout
,
447 "assert PMC-RESETOUT# signal",
451 int do_inta(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
454 printf("This command is only supported in non-monarch mode\n");
459 if (argv
[1][0] == '0') {
461 printf("inta# asserted\n");
462 out_be32((void*)GPIO1_TCR
,
463 in_be32((void*)GPIO1_TCR
) | GPIO1_INTA_FAKE
);
466 printf("inta# deasserted\n");
467 out_be32((void*)GPIO1_TCR
,
468 in_be32((void*)GPIO1_TCR
) & ~GPIO1_INTA_FAKE
);
471 printf("inta# is %s\n",
472 in_be32((void*)GPIO1_TCR
) & GPIO1_INTA_FAKE
?
473 "active" : "inactive");
479 "Assert/Deassert or query INTA# state in non-monarch mode",
484 int do_pmm(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
489 pciaddr
= simple_strtoul(argv
[1], NULL
, 16);
491 pciaddr
&= 0xf0000000;
493 /* map PCI address at 0xc0000000 in PLB space */
495 /* PMM1 Mask/Attribute - disabled b4 setting */
496 out32r(PCIL0_PMM1MA
, 0x00000000);
497 /* PMM1 Local Address */
498 out32r(PCIL0_PMM1LA
, 0xc0000000);
499 /* PMM1 PCI Low Address */
500 out32r(PCIL0_PMM1PCILA
, pciaddr
);
501 /* PMM1 PCI High Address */
502 out32r(PCIL0_PMM1PCIHA
, 0x00000000);
503 /* 256MB + No prefetching, and enable region */
504 out32r(PCIL0_PMM1MA
, 0xf0000001);
506 printf("Usage:\npmm %s\n", cmdtp
->help
);
512 "Setup pmm[1] registers",
513 "<pciaddr> (pciaddr will be aligned to 256MB)"
516 #if defined(CONFIG_SYS_EEPROM_WREN)
517 int do_eep_wren(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
519 int query
= argc
== 1;
523 /* Query write access state. */
524 state
= eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR
, -1);
526 puts("Query of write access state failed.\n");
528 printf("Write access for device 0x%0x is %sabled.\n",
529 CONFIG_SYS_I2C_EEPROM_ADDR
, state
? "en" : "dis");
533 if ('0' == argv
[1][0]) {
534 /* Disable write access. */
535 state
= eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR
, 0);
537 /* Enable write access. */
538 state
= eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR
, 1);
541 puts("Setup of write access state failed.\n");
547 U_BOOT_CMD(eepwren
, 2, 0, do_eep_wren
,
548 "Enable / disable / query EEPROM write access",
551 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
553 #endif /* CONFIG_CMD_BSP */