2 * (C) Copyright 2007-2008
3 * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/cache.h>
28 #include <asm/processor.h>
29 #if defined(CONFIG_LOGBUFFER)
36 int bootstrap_eeprom_write(unsigned dev_addr
, unsigned offset
,
37 uchar
*buffer
, unsigned cnt
);
38 int eeprom_write_enable(unsigned dev_addr
, int state
);
40 DECLARE_GLOBAL_DATA_PTR
;
42 #if defined(CONFIG_CMD_BSP)
44 static int got_fifoirq
;
47 int fpga_interrupt(u32 arg
)
49 pmc440_fpga_t
*fpga
= (pmc440_fpga_t
*)arg
;
50 int rc
= -1; /* not for us */
51 u32 status
= FPGA_IN32(&fpga
->status
);
53 /* check for interrupt from fifo module */
54 if (status
& STATUS_FIFO_ISF
) {
55 /* disable this int source */
56 FPGA_OUT32(&fpga
->hostctrl
, HOSTCTRL_FIFOIE_GATE
);
58 got_fifoirq
= 1; /* trigger backend */
61 if (status
& STATUS_HOST_ISF
) {
62 FPGA_OUT32(&fpga
->hostctrl
, HOSTCTRL_HCINT_GATE
);
70 int do_waithci(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
72 pmc440_fpga_t
*fpga
= (pmc440_fpga_t
*)FPGA_BA
;
76 FPGA_CLRBITS(&fpga
->ctrla
, CTRL_HOST_IE
);
77 FPGA_OUT32(&fpga
->hostctrl
, HOSTCTRL_HCINT_GATE
);
79 irq_install_handler(IRQ0_FPGA
,
80 (interrupt_handler_t
*)fpga_interrupt
,
83 FPGA_SETBITS(&fpga
->ctrla
, CTRL_HOST_IE
);
86 /* Abort if ctrl-c was pressed */
93 printf("Got interrupt!\n");
95 FPGA_CLRBITS(&fpga
->ctrla
, CTRL_HOST_IE
);
96 irq_free_handler(IRQ0_FPGA
);
100 waithci
, 1, 1, do_waithci
,
101 "Wait for host control interrupt",
105 void dump_fifo(pmc440_fpga_t
*fpga
, int f
, int *n
)
109 while (!((ctrl
= FPGA_IN32(&fpga
->fifo
[f
].ctrl
)) & FIFO_EMPTY
)) {
110 printf("%5d %d %3d %08x",
111 (*n
)++, f
, ctrl
& (FIFO_LEVEL_MASK
| FIFO_FULL
),
112 FPGA_IN32(&fpga
->fifo
[f
].data
));
113 if (ctrl
& FIFO_OVERFLOW
) {
114 printf(" OVERFLOW\n");
115 FPGA_CLRBITS(&fpga
->fifo
[f
].ctrl
, FIFO_OVERFLOW
);
121 int do_fifo(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
123 pmc440_fpga_t
*fpga
= (pmc440_fpga_t
*)FPGA_BA
;
127 char str
[] = "\\|/-";
134 /* print all fifos status information */
135 printf("fifo level status\n");
136 printf("______________________________\n");
137 for (i
=0; i
<FIFO_COUNT
; i
++) {
138 ctrl
= FPGA_IN32(&fpga
->fifo
[i
].ctrl
);
139 printf(" %d %3d %s%s%s %s\n",
140 i
, ctrl
& (FIFO_LEVEL_MASK
| FIFO_FULL
),
141 ctrl
& FIFO_FULL
? "FULL " : "",
142 ctrl
& FIFO_EMPTY
? "EMPTY " : "",
143 ctrl
& (FIFO_FULL
|FIFO_EMPTY
) ? "" : "NOT EMPTY",
144 ctrl
& FIFO_OVERFLOW
? "OVERFLOW" : "");
149 /* completely read out fifo 'n' */
150 if (!strcmp(argv
[1],"read")) {
151 printf(" # fifo level data\n");
152 printf("______________________________\n");
154 for (i
=0; i
<FIFO_COUNT
; i
++)
155 dump_fifo(fpga
, i
, &n
);
157 } else if (!strcmp(argv
[1],"wait")) {
160 irq_install_handler(IRQ0_FPGA
,
161 (interrupt_handler_t
*)fpga_interrupt
,
164 printf(" # fifo level data\n");
165 printf("______________________________\n");
167 /* enable all fifo interrupts */
168 FPGA_OUT32(&fpga
->hostctrl
,
169 HOSTCTRL_FIFOIE_GATE
| HOSTCTRL_FIFOIE_FLAG
);
170 for (i
=0; i
<FIFO_COUNT
; i
++) {
171 /* enable interrupts from all fifos */
172 FPGA_SETBITS(&fpga
->fifo
[i
].ctrl
, FIFO_IE
);
177 while (!got_fifoirq
) {
179 if (!(count
% 100)) {
181 putc(0x08); /* backspace */
182 putc(str
[count2
% 4]);
185 /* Abort if ctrl-c was pressed */
186 if ((abort
= ctrlc())) {
195 /* simple fifo backend */
197 for (i
=0; i
<FIFO_COUNT
; i
++)
198 dump_fifo(fpga
, i
, &n
);
201 /* unmask global fifo irq */
202 FPGA_OUT32(&fpga
->hostctrl
,
203 HOSTCTRL_FIFOIE_GATE
|
204 HOSTCTRL_FIFOIE_FLAG
);
208 /* disable all fifo interrupts */
209 FPGA_OUT32(&fpga
->hostctrl
, HOSTCTRL_FIFOIE_GATE
);
210 for (i
=0; i
<FIFO_COUNT
; i
++)
211 FPGA_CLRBITS(&fpga
->fifo
[i
].ctrl
, FIFO_IE
);
213 irq_free_handler(IRQ0_FPGA
);
216 printf("Usage:\nfifo %s\n", cmdtp
->help
);
223 if (!strcmp(argv
[1],"write")) {
224 /* get fifo number or fifo address */
225 f
= simple_strtoul(argv
[2], NULL
, 16);
228 data
= simple_strtoul(argv
[3], NULL
, 16);
230 /* get optional count parameter */
233 n
= (int)simple_strtoul(argv
[4], NULL
, 10);
235 if (f
< FIFO_COUNT
) {
236 printf("writing %d x %08x to fifo %d\n",
239 FPGA_OUT32(&fpga
->fifo
[f
].data
, data
);
241 printf("writing %d x %08x to fifo port at "
248 printf("Usage:\nfifo %s\n", cmdtp
->help
);
254 printf("Usage:\nfifo %s\n", cmdtp
->help
);
261 "Fifo module operations",
263 "fifo write fifo(0..3) data [cnt=1]\n"
264 "fifo write address(>=4) data [cnt=1]\n"
265 " - without arguments: print all fifo's status\n"
266 " - with 'wait' argument: interrupt driven read from all fifos\n"
267 " - with 'read' argument: read current contents from all fifos\n"
268 " - with 'write' argument: write 'data' 'cnt' times to "
269 "'fifo' or 'address'\n"
272 int do_setup_bootstrap_eeprom(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
279 printf("Usage:\nsbe %s\n", cmdtp
->help
);
284 if (!strcmp(argv
[1], "400")) {
285 /* PLB=133MHz, PLB/PCI=3 */
286 printf("Bootstrapping for 400MHz\n");
291 } else if (!strcmp(argv
[1], "533")) {
292 /* PLB=133MHz, PLB/PCI=3 */
293 printf("Bootstrapping for 533MHz\n");
298 } else if (!strcmp(argv
[1], "667")) {
299 /* PLB=133MHz, PLB/PCI=3 */
300 printf("Bootstrapping for 667MHz\n");
306 printf("Usage:\nsbe %s\n", cmdtp
->help
);
315 else if (argv
[2][0]=='0')
322 delay
= simple_strtoul(argv
[3], NULL
, 10);
328 printf("Writing boot EEPROM ...\n");
329 if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR
,
330 0, (uchar
*)sdsdp
, count
) != 0)
331 printf("bootstrap_eeprom_write failed\n");
333 printf("done (dump via 'i2c md 52 0.1 14')\n");
338 sbe
, 4, 0, do_setup_bootstrap_eeprom
,
339 "setup bootstrap eeprom",
340 "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
343 #if defined(CONFIG_PRAM)
344 #include <environment.h>
345 extern env_t
*env_ptr
;
347 int do_painit(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
349 u32 pram
, nextbase
, base
;
356 pram
= simple_strtoul(v
, NULL
, 10);
358 printf("Error: pram undefined. Please define pram in KiB\n");
362 base
= gd
->bd
->bi_memsize
;
363 #if defined(CONFIG_LOGBUFFER)
364 base
-= LOGBUFF_LEN
+ LOGBUFF_OVERHEAD
;
367 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
369 param
= base
- (pram
<< 10);
370 printf("PARAM: @%08x\n", param
);
371 debug("memsize=0x%08x, base=0x%08x\n", gd
->bd
->bi_memsize
, base
);
373 /* clear entire PA ram */
374 memset((void*)param
, 0, (pram
<< 10));
376 /* reserve 4k for pointer field */
377 nextbase
= base
- 4096;
378 lptr
= (ulong
*)(base
);
381 * *(--lptr) = item_size;
382 * *(--lptr) = base - item_base = distance from field top;
385 /* env is first (4k aligned) */
386 nextbase
-= ((CONFIG_ENV_SIZE
+ 4096 - 1) & ~(4096 - 1));
387 memcpy((void*)nextbase
, env_ptr
, CONFIG_ENV_SIZE
);
388 *(--lptr
) = CONFIG_ENV_SIZE
; /* size */
389 *(--lptr
) = base
- nextbase
; /* offset | type=0 */
392 *(--lptr
) = nextbase
- param
; /* size */
393 *(--lptr
) = (base
- param
) | 126; /* offset | type=126 */
395 /* terminate pointer field */
396 *(--lptr
) = crc32(0, (void*)(base
- 0x10), 0x10);
397 *(--lptr
) = 0; /* offset=0 -> terminator */
401 painit
, 1, 1, do_painit
,
402 "prepare PciAccess system",
405 #endif /* CONFIG_PRAM */
407 int do_selfreset(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
409 in_be32((void*)CONFIG_SYS_RESET_BASE
);
413 selfreset
, 1, 1, do_selfreset
,
414 "assert self-reset# signal",
418 int do_resetout(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
420 pmc440_fpga_t
*fpga
= (pmc440_fpga_t
*)FPGA_BA
;
422 /* requiers bootet FPGA and PLD_IOEN_N active */
423 if (in_be32((void*)GPIO1_OR
) & GPIO1_IOEN_N
) {
424 printf("Error: resetout requires a bootet FPGA\n");
429 if (argv
[1][0] == '0') {
431 printf("PMC-RESETOUT# asserted\n");
432 FPGA_OUT32(&fpga
->hostctrl
,
433 HOSTCTRL_PMCRSTOUT_GATE
);
436 printf("PMC-RESETOUT# deasserted\n");
437 FPGA_OUT32(&fpga
->hostctrl
,
438 HOSTCTRL_PMCRSTOUT_GATE
|
439 HOSTCTRL_PMCRSTOUT_FLAG
);
442 printf("PMC-RESETOUT# is %s\n",
443 FPGA_IN32(&fpga
->hostctrl
) & HOSTCTRL_PMCRSTOUT_FLAG
?
444 "inactive" : "active");
450 resetout
, 2, 1, do_resetout
,
451 "assert PMC-RESETOUT# signal",
455 int do_inta(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
458 printf("This command is only supported in non-monarch mode\n");
463 if (argv
[1][0] == '0') {
465 printf("inta# asserted\n");
466 out_be32((void*)GPIO1_TCR
,
467 in_be32((void*)GPIO1_TCR
) | GPIO1_INTA_FAKE
);
470 printf("inta# deasserted\n");
471 out_be32((void*)GPIO1_TCR
,
472 in_be32((void*)GPIO1_TCR
) & ~GPIO1_INTA_FAKE
);
475 printf("inta# is %s\n",
476 in_be32((void*)GPIO1_TCR
) & GPIO1_INTA_FAKE
?
477 "active" : "inactive");
483 "Assert/Deassert or query INTA# state in non-monarch mode",
488 int do_pmm(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
493 pciaddr
= simple_strtoul(argv
[1], NULL
, 16);
495 pciaddr
&= 0xf0000000;
497 /* map PCI address at 0xc0000000 in PLB space */
499 /* PMM1 Mask/Attribute - disabled b4 setting */
500 out32r(PCIX0_PMM1MA
, 0x00000000);
501 /* PMM1 Local Address */
502 out32r(PCIX0_PMM1LA
, 0xc0000000);
503 /* PMM1 PCI Low Address */
504 out32r(PCIX0_PMM1PCILA
, pciaddr
);
505 /* PMM1 PCI High Address */
506 out32r(PCIX0_PMM1PCIHA
, 0x00000000);
507 /* 256MB + No prefetching, and enable region */
508 out32r(PCIX0_PMM1MA
, 0xf0000001);
510 printf("Usage:\npmm %s\n", cmdtp
->help
);
516 "Setup pmm[1] registers",
517 "<pciaddr> (pciaddr will be aligned to 256MB)\n"
520 #if defined(CONFIG_SYS_EEPROM_WREN)
521 int do_eep_wren(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
523 int query
= argc
== 1;
527 /* Query write access state. */
528 state
= eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR
, -1);
530 puts("Query of write access state failed.\n");
532 printf("Write access for device 0x%0x is %sabled.\n",
533 CONFIG_SYS_I2C_EEPROM_ADDR
, state
? "en" : "dis");
537 if ('0' == argv
[1][0]) {
538 /* Disable write access. */
539 state
= eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR
, 0);
541 /* Enable write access. */
542 state
= eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR
, 1);
545 puts("Setup of write access state failed.\n");
551 U_BOOT_CMD(eepwren
, 2, 0, do_eep_wren
,
552 "Enable / disable / query EEPROM write access",
554 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
556 #endif /* CONFIG_CMD_BSP */