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1 /*
2 * vme8349.c -- esd VME8349 board support
3 *
4 * Copyright (c) 2008-2009 esd gmbh.
5 *
6 * (C) Copyright 2006
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
10 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 *
30 */
31
32 #include <common.h>
33 #include <ioports.h>
34 #include <mpc83xx.h>
35 #include <asm/mpc8349_pci.h>
36 #if defined(CONFIG_OF_LIBFDT)
37 #include <libfdt.h>
38 #endif
39 #include <asm/io.h>
40 #include <asm/mmu.h>
41 #include <spd.h>
42 #include <spd_sdram.h>
43 #include <i2c.h>
44 #include <netdev.h>
45
46 void ddr_enable_ecc(unsigned int dram_size);
47
48 phys_size_t initdram(int board_type)
49 {
50 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
51 u32 msize = 0;
52
53 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
54 return -1;
55
56 /* DDR SDRAM - Main memory */
57 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
58
59 msize = spd_sdram();
60
61 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
62 /*
63 * Initialize and enable DDR ECC.
64 */
65 ddr_enable_ecc(msize * 1024 * 1024);
66 #endif
67
68 /* Now check memory size (after ECC is initialized) */
69 msize = get_ram_size(0, msize);
70
71 /* return total bus SDRAM size(bytes) -- DDR */
72 return msize * 1024 * 1024;
73 }
74
75 int checkboard(void)
76 {
77 #ifdef VME_CADDY2
78 puts("Board: esd VME-CADDY/2\n");
79 #else
80 puts("Board: esd VME-CPU/8349\n");
81 #endif
82
83 return 0;
84 }
85
86 #ifdef VME_CADDY2
87 int board_eth_init(bd_t *bis)
88 {
89 return pci_eth_init(bis);
90 }
91 #endif
92
93 #if defined(CONFIG_OF_BOARD_SETUP)
94 void ft_board_setup(void *blob, bd_t *bd)
95 {
96 ft_cpu_setup(blob, bd);
97
98 #ifdef CONFIG_PCI
99 ft_pci_setup(blob, bd);
100 #endif
101 }
102 #endif
103
104 int misc_init_r()
105 {
106 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
107
108 clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
109
110 return 0;
111 }
112
113 /*
114 * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
115 * and VME-CADDY/2) have different SDRAM configurations.
116 */
117 #ifdef VME_CADDY2
118 #define SMALL_RAM 0xff
119 #define LARGE_RAM 0x00
120 #else
121 #define SMALL_RAM 0x00
122 #define LARGE_RAM 0xff
123 #endif
124
125 #define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
126
127 static spd_eeprom_t default_spd_eeprom = {
128 SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
129 SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
130 SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
131 SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
132 SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
133 SPD_VAL(0x00, 0x00), /* 05 */
134 SPD_VAL(0x40, 0x40), /* 06 */
135 SPD_VAL(0x00, 0x00), /* 07 */
136 SPD_VAL(0x05, 0x05), /* 08 */
137 SPD_VAL(0x30, 0x30), /* 09 */
138 SPD_VAL(0x45, 0x45), /* 10 */
139 SPD_VAL(0x02, 0x02), /* 11 ecc used */
140 SPD_VAL(0x82, 0x82), /* 12 */
141 SPD_VAL(0x10, 0x10), /* 13 */
142 SPD_VAL(0x08, 0x08), /* 14 */
143 SPD_VAL(0x00, 0x00), /* 15 */
144 SPD_VAL(0x0c, 0x0c), /* 16 */
145 SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
146 SPD_VAL(0x38, 0x38), /* 18 */
147 SPD_VAL(0x00, 0x00), /* 19 */
148 SPD_VAL(0x02, 0x02), /* 20 */
149 SPD_VAL(0x00, 0x00), /* 21 */
150 SPD_VAL(0x03, 0x03), /* 22 */
151 SPD_VAL(0x3d, 0x3d), /* 23 */
152 SPD_VAL(0x45, 0x45), /* 24 */
153 SPD_VAL(0x50, 0x50), /* 25 */
154 SPD_VAL(0x45, 0x45), /* 26 */
155 SPD_VAL(0x3c, 0x3c), /* 27 */
156 SPD_VAL(0x28, 0x28), /* 28 */
157 SPD_VAL(0x3c, 0x3c), /* 29 */
158 SPD_VAL(0x2d, 0x2d), /* 30 */
159 SPD_VAL(0x20, 0x80), /* 31 */
160 SPD_VAL(0x20, 0x20), /* 32 */
161 SPD_VAL(0x27, 0x27), /* 33 */
162 SPD_VAL(0x10, 0x10), /* 34 */
163 SPD_VAL(0x17, 0x17), /* 35 */
164 SPD_VAL(0x3c, 0x3c), /* 36 */
165 SPD_VAL(0x1e, 0x1e), /* 37 */
166 SPD_VAL(0x1e, 0x1e), /* 38 */
167 SPD_VAL(0x00, 0x00), /* 39 */
168 SPD_VAL(0x00, 0x06), /* 40 */
169 SPD_VAL(0x37, 0x37), /* 41 */
170 SPD_VAL(0x4b, 0x7f), /* 42 */
171 SPD_VAL(0x80, 0x80), /* 43 */
172 SPD_VAL(0x18, 0x18), /* 44 */
173 SPD_VAL(0x22, 0x22), /* 45 */
174 SPD_VAL(0x00, 0x00), /* 46 */
175 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
176 SPD_VAL(0x10, 0x10), /* 62 */
177 SPD_VAL(0x7e, 0x1d), /* 63 */
178 { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
179 SPD_VAL(0x00, 0x00), /* 72 */
180 #ifdef VME_CADDY2
181 { "vme-caddy/2 ram " }
182 #else
183 { "vme-cpu/2 ram " }
184 #endif
185 };
186
187 int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
188 {
189 int old_bus = I2C_GET_BUS();
190 unsigned int l, sum;
191 int valid = 0;
192
193 I2C_SET_BUS(0);
194
195 if (i2c_read(chip, addr, alen, buffer, len) == 0)
196 if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
197 sum = 0;
198 for (l = 0; l < 63; l++)
199 sum = (sum + buffer[l]) & 0xff;
200 if (sum == buffer[63])
201 valid = 1;
202 else
203 printf("Invalid checksum in EEPROM %02x %02x\n",
204 sum, buffer[63]);
205 }
206
207 if (valid == 0) {
208 memcpy(buffer, (void *)&default_spd_eeprom, len);
209 sum = 0;
210 for (l = 0; l < 63; l++)
211 sum = (sum + buffer[l]) & 0xff;
212 if (sum != buffer[63])
213 printf("Invalid checksum in FLASH %02x %02x\n",
214 sum, buffer[63]);
215 buffer[63] = sum;
216 }
217
218 I2C_SET_BUS(old_bus);
219
220 return 0;
221 }