board/esd/voh405/voh405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/processor.h>
  27 #include <command.h>
  28 #include <malloc.h>
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 #if 0
  33 #define FPGA_DEBUG
  34 #endif
  35
  36 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  37 extern void lxt971_no_sleep(void);
  38
  39 /* fpga configuration data - gzip compressed and generated by bin2c */
  40 const unsigned char fpgadata[] =
  41 {
  42 #include "fpgadata.c"
  43 };
  44
  45 /*
  46  * include common fpga code (for esd boards)
  47  */
  48 #include "../common/fpga.c"
  49
  50
  51 /* Prototypes */
  52 int gunzip(void *, int, unsigned char *, unsigned long *);
  53
  54
  55 /* logo bitmap data - gzip compressed and generated by bin2c */
  56 unsigned char logo_bmp_320[] =
  57 {
  58 #include "logo_320_240_4bpp.c"
  59 };
  60
  61 unsigned char logo_bmp_640[] =
  62 {
  63 #include "logo_640_480_24bpp.c"
  64 };
  65
  66
  67 /*
  68  * include common lcd code (for esd boards)
  69  */
  70 #include "../common/lcd.c"
  71
  72 #include "../common/s1d13704_320_240_4bpp.h"
  73 #include "../common/s1d13806_320_240_4bpp.h"
  74 #include "../common/s1d13806_640_480_16bpp.h"
  75
  76
  77 int board_early_init_f (void)
  78 {
  79         /*
  80          * IRQ 0-15  405GP internally generated; active high; level sensitive
  81          * IRQ 16    405GP internally generated; active low; level sensitive
  82          * IRQ 17-24 RESERVED
  83          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  84          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  85          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  86          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  87          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  88          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  89          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  90          */
  91         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  92         mtdcr(uicer, 0x00000000);       /* disable all ints */
  93         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
  94         mtdcr(uicpr, 0xFFFFFFB5);       /* set int polarities */
  95         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
  96         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  97         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
  98
  99         /*
 100          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
 101          */
 102         mtebc (epcr, 0xa8400000); /* ebc always driven */
 103
 104         return 0;
 105 }
 106
 107
 108 int misc_init_f (void)
 109 {
 110         return 0;  /* dummy implementation */
 111 }
 112
 113
 114 int misc_init_r (void)
 115 {
 116         unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 117         unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 118         unsigned short *lcd_contrast =
 119                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
 120         unsigned short *lcd_backlight =
 121                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
 122         unsigned char *dst;
 123         ulong len = sizeof(fpgadata);
 124         int status;
 125         int index;
 126         int i;
 127         char *str;
 128
 129         dst = malloc(CFG_FPGA_MAX_SIZE);
 130         if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 131                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 132                 do_reset (NULL, 0, 0, NULL);
 133         }
 134
 135         status = fpga_boot(dst, len);
 136         if (status != 0) {
 137                 printf("\nFPGA: Booting failed ");
 138                 switch (status) {
 139                 case ERROR_FPGA_PRG_INIT_LOW:
 140                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 141                         break;
 142                 case ERROR_FPGA_PRG_INIT_HIGH:
 143                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 144                         break;
 145                 case ERROR_FPGA_PRG_DONE:
 146                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 147                         break;
 148                 }
 149
 150                 /* display infos on fpgaimage */
 151                 index = 15;
 152                 for (i=0; i<4; i++) {
 153                         len = dst[index];
 154                         printf("FPGA: %s\n", &(dst[index+1]));
 155                         index += len+3;
 156                 }
 157                 putc ('\n');
 158                 /* delayed reboot */
 159                 for (i=20; i>0; i--) {
 160                         printf("Rebooting in %2d seconds \r",i);
 161                         for (index=0;index<1000;index++)
 162                                 udelay(1000);
 163                 }
 164                 putc ('\n');
 165                 do_reset(NULL, 0, 0, NULL);
 166         }
 167
 168         puts("FPGA:  ");
 169
 170         /* display infos on fpgaimage */
 171         index = 15;
 172         for (i=0; i<4; i++) {
 173                 len = dst[index];
 174                 printf("%s ", &(dst[index+1]));
 175                 index += len+3;
 176         }
 177         putc ('\n');
 178
 179         free(dst);
 180
 181         /*
 182          * Reset FPGA via FPGA_INIT pin
 183          */
 184         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
 185         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
 186         udelay(1000); /* wait 1ms */
 187         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT);   /* reset high */
 188         udelay(1000); /* wait 1ms */
 189
 190         /*
 191          * Reset external DUARTs
 192          */
 193         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
 194         udelay(10); /* wait 10us */
 195         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
 196         udelay(1000); /* wait 1ms */
 197
 198         /*
 199          * Set NAND-FLASH GPIO signals to default
 200          */
 201         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
 202         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
 203
 204         /*
 205          * Setup EEPROM write protection
 206          */
 207         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
 208         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
 209
 210         /*
 211          * Enable interrupts in exar duart mcr[3]
 212          */
 213         out_8(duart0_mcr, 0x08);
 214         out_8(duart1_mcr, 0x08);
 215
 216         /*
 217          * Init lcd interface and display logo
 218          */
 219         str = getenv("bd_type");
 220         if (strcmp(str, "voh405_bw") == 0) {
 221                 lcd_setup(0, 1);
 222                 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
 223                          regs_13704_320_240_4bpp,
 224                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 225                          logo_bmp_320, sizeof(logo_bmp_320));
 226         } else if (strcmp(str, "voh405_bwbw") == 0) {
 227                 lcd_setup(0, 1);
 228                 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
 229                          regs_13704_320_240_4bpp,
 230                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 231                          logo_bmp_320, sizeof(logo_bmp_320));
 232                 lcd_setup(1, 1);
 233                 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
 234                          regs_13806_320_240_4bpp,
 235                          sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
 236                          logo_bmp_320, sizeof(logo_bmp_320));
 237         } else if (strcmp(str, "voh405_bwc") == 0) {
 238                 lcd_setup(0, 1);
 239                 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
 240                          regs_13704_320_240_4bpp,
 241                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 242                          logo_bmp_320, sizeof(logo_bmp_320));
 243                 lcd_setup(1, 0);
 244                 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
 245                          regs_13806_640_480_16bpp,
 246                          sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 247                          logo_bmp_640, sizeof(logo_bmp_640));
 248         } else {
 249                 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 250                 return 0;
 251         }
 252
 253         /*
 254          * Set invert bit in small lcd controller
 255          */
 256         out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
 257               in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
 258
 259         /*
 260          * Set default contrast voltage on epson vga controller
 261          */
 262         out_be16(lcd_contrast, 0x4646);
 263
 264         /*
 265          * Enable backlight
 266          */
 267         out_be16(lcd_backlight, 0xffff);
 268
 269         /*
 270          * Enable external I2C bus
 271          */
 272         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
 273
 274         return (0);
 275 }
 276
 277
 278 /*
 279  * Check Board Identity:
 280  */
 281
 282 int checkboard (void)
 283 {
 284         char str[64];
 285         int i = getenv_r ("serial#", str, sizeof(str));
 286
 287         puts ("Board: ");
 288
 289         if (i == -1) {
 290                 puts ("### No HW ID - assuming VOH405");
 291         } else {
 292                 puts(str);
 293         }
 294
 295         if (getenv_r("bd_type", str, sizeof(str)) != -1) {
 296                 printf(" (%s)", str);
 297         } else {
 298                 puts(" (Missing bd_type!)");
 299         }
 300
 301         putc ('\n');
 302
 303         return 0;
 304 }
 305
 306 /* ------------------------------------------------------------------------- */
 307
 308 long int initdram (int board_type)
 309 {
 310         unsigned long val;
 311
 312         mtdcr(memcfga, mem_mb0cf);
 313         val = mfdcr(memcfgd);
 314
 315 #if 0
 316         printf("\nmb0cf=%x\n", val); /* test-only */
 317         printf("strap=%x\n", mfdcr(strap)); /* test-only */
 318 #endif
 319
 320         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 321 }
 322
 323 /* ------------------------------------------------------------------------- */
 324
 325 int testdram (void)
 326 {
 327         /* TODO: XXX XXX XXX */
 328         printf ("test: 16 MB - ok\n");
 329
 330         return (0);
 331 }
 332
 333 /* ------------------------------------------------------------------------- */
 334
 335 #ifdef CONFIG_IDE_RESET
 336 void ide_set_reset(int on)
 337 {
 338         volatile unsigned short *fpga_mode =
 339                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 340
 341         /*
 342          * Assert or deassert CompactFlash Reset Pin
 343          */
 344         if (on) {               /* assert RESET */
 345                 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
 346         } else {                /* release RESET */
 347                 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
 348         }
 349 }
 350 #endif /* CONFIG_IDE_RESET */
 351
 352 #if defined(CONFIG_RESET_PHY_R)
 353 void reset_phy(void)
 354 {
 355 #ifdef CONFIG_LXT971_NO_SLEEP
 356
 357         /*
 358          * Disable sleep mode in LXT971
 359          */
 360         lxt971_no_sleep();
 361 #endif
 362 }
 363 #endif
 364
 365 #if defined(CFG_EEPROM_WREN)
 366 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 367  *         <state>     -1: deliver current state
 368  *                     0: disable write
 369  *                     1: enable write
 370  *  Returns:           -1: wrong device address
 371  *                      0: dis-/en- able done
 372  *                   0/1: current state if <state> was -1.
 373  */
 374 int eeprom_write_enable (unsigned dev_addr, int state)
 375 {
 376         if (CFG_I2C_EEPROM_ADDR != dev_addr) {
 377                 return -1;
 378         } else {
 379                 switch (state) {
 380                 case 1:
 381                         /* Enable write access, clear bit GPIO0. */
 382                         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
 383                         state = 0;
 384                         break;
 385                 case 0:
 386                         /* Disable write access, set bit GPIO0. */
 387                         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
 388                         state = 0;
 389                         break;
 390                 default:
 391                         /* Read current status back. */
 392                         state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
 393                         break;
 394                 }
 395         }
 396         return state;
 397 }
 398
 399 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 400 {
 401         int query = argc == 1;
 402         int state = 0;
 403
 404         if (query) {
 405                 /* Query write access state. */
 406                 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
 407                 if (state < 0) {
 408                         puts ("Query of write access state failed.\n");
 409                 } else {
 410                         printf ("Write access for device 0x%0x is %sabled.\n",
 411                                 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
 412                         state = 0;
 413                 }
 414         } else {
 415                 if ('0' == argv[1][0]) {
 416                         /* Disable write access. */
 417                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
 418                 } else {
 419                         /* Enable write access. */
 420                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
 421                 }
 422                 if (state < 0) {
 423                         puts ("Setup of write access state failed.\n");
 424                 }
 425         }
 426
 427         return state;
 428 }
 429
 430 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 431            "eepwren - Enable / disable / query EEPROM write access\n",
 432            NULL);
 433 #endif /* #if defined(CFG_EEPROM_WREN) */