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git.ipfire.org Git - people/ms/u-boot.git/blob - board/esd/voh405/voh405.c
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 /* ------------------------------------------------------------------------- */
35 extern int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[]);
37 /* fpga configuration data - gzip compressed and generated by bin2c */
38 const unsigned char fpgadata
[] =
44 * include common fpga code (for esd boards)
46 #include "../common/fpga.c"
50 int gunzip(void *, int, unsigned char *, unsigned long *);
53 int board_early_init_f (void)
56 * IRQ 0-15 405GP internally generated; active high; level sensitive
57 * IRQ 16 405GP internally generated; active low; level sensitive
59 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
60 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
61 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
62 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
63 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
64 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
65 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
67 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
68 mtdcr(uicer
, 0x00000000); /* disable all ints */
69 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
70 mtdcr(uicpr
, 0xFFFFFFB5); /* set int polarities */
71 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
72 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority*/
73 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
76 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
78 mtebc (epcr
, 0xa8400000); /* ebc always driven */
84 /* ------------------------------------------------------------------------- */
86 int misc_init_f (void)
88 return 0; /* dummy implementation */
92 int misc_init_r (void)
94 volatile unsigned char *duart0_mcr
= (unsigned char *)((ulong
)DUART0_BA
+ 4);
95 volatile unsigned char *duart1_mcr
= (unsigned char *)((ulong
)DUART1_BA
+ 4);
96 volatile unsigned short *lcd_reg
=
97 (unsigned short *)((ulong
)CFG_FPGA_BASE_ADDR
+ CFG_FPGA_CTRL
+ 4);
99 ulong len
= sizeof(fpgadata
);
104 dst
= malloc(CFG_FPGA_MAX_SIZE
);
105 if (gunzip (dst
, CFG_FPGA_MAX_SIZE
, (uchar
*)fpgadata
, &len
) != 0) {
106 printf ("GUNZIP ERROR - must RESET board to recover\n");
107 do_reset (NULL
, 0, 0, NULL
);
110 status
= fpga_boot(dst
, len
);
112 printf("\nFPGA: Booting failed ");
114 case ERROR_FPGA_PRG_INIT_LOW
:
115 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
117 case ERROR_FPGA_PRG_INIT_HIGH
:
118 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
120 case ERROR_FPGA_PRG_DONE
:
121 printf("(Timeout: DONE not high after programming FPGA)\n ");
125 /* display infos on fpgaimage */
127 for (i
=0; i
<4; i
++) {
129 printf("FPGA: %s\n", &(dst
[index
+1]));
134 for (i
=20; i
>0; i
--) {
135 printf("Rebooting in %2d seconds \r",i
);
136 for (index
=0;index
<1000;index
++)
140 do_reset(NULL
, 0, 0, NULL
);
145 /* display infos on fpgaimage */
147 for (i
=0; i
<4; i
++) {
149 printf("%s ", &(dst
[index
+1]));
157 * Reset FPGA via FPGA_DATA pin
159 SET_FPGA(FPGA_PRG
| FPGA_CLK
);
160 udelay(1000); /* wait 1ms */
161 SET_FPGA(FPGA_PRG
| FPGA_CLK
| FPGA_DATA
);
162 udelay(1000); /* wait 1ms */
165 * Reset external DUARTs
167 out32(GPIO0_OR
, in32(GPIO0_OR
) | CFG_DUART_RST
); /* set reset to high */
168 udelay(10); /* wait 10us */
169 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~CFG_DUART_RST
); /* set reset to low */
170 udelay(1000); /* wait 1ms */
173 * Set NAND-FLASH GPIO signals to default
175 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~(CFG_NAND_CLE
| CFG_NAND_ALE
));
176 out32(GPIO0_OR
, in32(GPIO0_OR
) | CFG_NAND_CE
);
179 * Enable interrupts in exar duart mcr[3]
185 * Set default contrast voltage on epson vga controller
194 * Check Board Identity:
197 int checkboard (void)
199 unsigned char str
[64];
200 int i
= getenv_r ("serial#", str
, sizeof(str
));
205 puts ("### No HW ID - assuming VOH405");
215 /* ------------------------------------------------------------------------- */
217 long int initdram (int board_type
)
221 mtdcr(memcfga
, mem_mb0cf
);
222 val
= mfdcr(memcfgd
);
225 printf("\nmb0cf=%x\n", val
); /* test-only */
226 printf("strap=%x\n", mfdcr(strap
)); /* test-only */
229 return (4*1024*1024 << ((val
& 0x000e0000) >> 17));
232 /* ------------------------------------------------------------------------- */
236 /* TODO: XXX XXX XXX */
237 printf ("test: 16 MB - ok\n");
242 /* ------------------------------------------------------------------------- */
244 #ifdef CONFIG_IDE_RESET
245 void ide_set_reset(int on
)
247 volatile unsigned short *fpga_mode
=
248 (unsigned short *)((ulong
)CFG_FPGA_BASE_ADDR
+ CFG_FPGA_CTRL
);
251 * Assert or deassert CompactFlash Reset Pin
253 if (on
) { /* assert RESET */
254 *fpga_mode
&= ~(CFG_FPGA_CTRL_CF_RESET
);
255 } else { /* release RESET */
256 *fpga_mode
|= CFG_FPGA_CTRL_CF_RESET
;
259 #endif /* CONFIG_IDE_RESET */
262 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
263 #include <linux/mtd/nand.h>
264 extern struct nand_chip nand_dev_desc
[CFG_MAX_NAND_DEVICE
];
268 nand_probe(CFG_NAND_BASE
);
269 if (nand_dev_desc
[0].ChipID
!= NAND_ChipID_UNKNOWN
) {
270 print_size(nand_dev_desc
[0].totlen
, "\n");