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git.ipfire.org Git - people/ms/u-boot.git/blob - board/esd/voh405/voh405.c
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 /* ------------------------------------------------------------------------- */
35 extern int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[]);
36 extern void lxt971_no_sleep(void);
38 /* fpga configuration data - gzip compressed and generated by bin2c */
39 const unsigned char fpgadata
[] =
45 * include common fpga code (for esd boards)
47 #include "../common/fpga.c"
51 int gunzip(void *, int, unsigned char *, unsigned long *);
54 /* logo bitmap data - gzip compressed and generated by bin2c */
55 unsigned char logo_bmp_320
[] =
57 #include "logo_320_240_4bpp.c"
60 unsigned char logo_bmp_640
[] =
62 #include "logo_640_480_24bpp.c"
67 * include common lcd code (for esd boards)
69 #include "../common/lcd.c"
71 #include "../common/s1d13704_320_240_4bpp.h"
72 #include "../common/s1d13806_320_240_4bpp.h"
73 #include "../common/s1d13806_640_480_16bpp.h"
76 int board_early_init_f (void)
79 * IRQ 0-15 405GP internally generated; active high; level sensitive
80 * IRQ 16 405GP internally generated; active low; level sensitive
82 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
83 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
84 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
85 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
86 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
87 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
88 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
90 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
91 mtdcr(uicer
, 0x00000000); /* disable all ints */
92 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
93 mtdcr(uicpr
, 0xFFFFFFB5); /* set int polarities */
94 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
95 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority*/
96 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
99 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
101 mtebc (epcr
, 0xa8400000); /* ebc always driven */
107 int misc_init_f (void)
109 return 0; /* dummy implementation */
113 int misc_init_r (void)
115 volatile unsigned char *duart0_mcr
= (unsigned char *)((ulong
)DUART0_BA
+ 4);
116 volatile unsigned char *duart1_mcr
= (unsigned char *)((ulong
)DUART1_BA
+ 4);
117 volatile unsigned short *lcd_contrast
=
118 (unsigned short *)((ulong
)CFG_FPGA_BASE_ADDR
+ CFG_FPGA_CTRL
+ 4);
119 volatile unsigned short *lcd_backlight
=
120 (unsigned short *)((ulong
)CFG_FPGA_BASE_ADDR
+ CFG_FPGA_CTRL
+ 6);
122 ulong len
= sizeof(fpgadata
);
128 dst
= malloc(CFG_FPGA_MAX_SIZE
);
129 if (gunzip (dst
, CFG_FPGA_MAX_SIZE
, (uchar
*)fpgadata
, &len
) != 0) {
130 printf ("GUNZIP ERROR - must RESET board to recover\n");
131 do_reset (NULL
, 0, 0, NULL
);
134 status
= fpga_boot(dst
, len
);
136 printf("\nFPGA: Booting failed ");
138 case ERROR_FPGA_PRG_INIT_LOW
:
139 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
141 case ERROR_FPGA_PRG_INIT_HIGH
:
142 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
144 case ERROR_FPGA_PRG_DONE
:
145 printf("(Timeout: DONE not high after programming FPGA)\n ");
149 /* display infos on fpgaimage */
151 for (i
=0; i
<4; i
++) {
153 printf("FPGA: %s\n", &(dst
[index
+1]));
158 for (i
=20; i
>0; i
--) {
159 printf("Rebooting in %2d seconds \r",i
);
160 for (index
=0;index
<1000;index
++)
164 do_reset(NULL
, 0, 0, NULL
);
169 /* display infos on fpgaimage */
171 for (i
=0; i
<4; i
++) {
173 printf("%s ", &(dst
[index
+1]));
181 * Reset FPGA via FPGA_INIT pin
183 out32(GPIO0_TCR
, in32(GPIO0_TCR
) | FPGA_INIT
); /* setup FPGA_INIT as output */
184 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~FPGA_INIT
); /* reset low */
185 udelay(1000); /* wait 1ms */
186 out32(GPIO0_OR
, in32(GPIO0_OR
) | FPGA_INIT
); /* reset high */
187 udelay(1000); /* wait 1ms */
190 * Reset external DUARTs
192 out32(GPIO0_OR
, in32(GPIO0_OR
) | CFG_DUART_RST
); /* set reset to high */
193 udelay(10); /* wait 10us */
194 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~CFG_DUART_RST
); /* set reset to low */
195 udelay(1000); /* wait 1ms */
198 * Enable interrupts in exar duart mcr[3]
204 * Init lcd interface and display logo
206 str
= getenv("bd_type");
207 if (strcmp(str
, "voh405_bw") == 0) {
209 lcd_init((uchar
*)CFG_LCD_SMALL_REG
, (uchar
*)CFG_LCD_SMALL_MEM
,
210 regs_13704_320_240_4bpp
,
211 sizeof(regs_13704_320_240_4bpp
)/sizeof(regs_13704_320_240_4bpp
[0]),
212 logo_bmp_320
, sizeof(logo_bmp_320
));
213 } else if (strcmp(str
, "voh405_bwbw") == 0) {
215 lcd_init((uchar
*)CFG_LCD_SMALL_REG
, (uchar
*)CFG_LCD_SMALL_MEM
,
216 regs_13704_320_240_4bpp
,
217 sizeof(regs_13704_320_240_4bpp
)/sizeof(regs_13704_320_240_4bpp
[0]),
218 logo_bmp_320
, sizeof(logo_bmp_320
));
220 lcd_init((uchar
*)CFG_LCD_BIG_REG
, (uchar
*)CFG_LCD_BIG_MEM
,
221 regs_13806_320_240_4bpp
,
222 sizeof(regs_13806_320_240_4bpp
)/sizeof(regs_13806_320_240_4bpp
[0]),
223 logo_bmp_320
, sizeof(logo_bmp_320
));
224 } else if (strcmp(str
, "voh405_bwc") == 0) {
226 lcd_init((uchar
*)CFG_LCD_SMALL_REG
, (uchar
*)CFG_LCD_SMALL_MEM
,
227 regs_13704_320_240_4bpp
,
228 sizeof(regs_13704_320_240_4bpp
)/sizeof(regs_13704_320_240_4bpp
[0]),
229 logo_bmp_320
, sizeof(logo_bmp_320
));
231 lcd_init((uchar
*)CFG_LCD_BIG_REG
, (uchar
*)CFG_LCD_BIG_MEM
,
232 regs_13806_640_480_16bpp
,
233 sizeof(regs_13806_640_480_16bpp
)/sizeof(regs_13806_640_480_16bpp
[0]),
234 logo_bmp_640
, sizeof(logo_bmp_640
));
236 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str
);
241 * Set invert bit in small lcd controller
243 *(unsigned char *)(CFG_LCD_SMALL_REG
+ 2) |= 0x01;
246 * Set default contrast voltage on epson vga controller
248 *lcd_contrast
= 0x4646;
253 *lcd_backlight
= 0xffff;
260 * Check Board Identity:
263 int checkboard (void)
266 int i
= getenv_r ("serial#", str
, sizeof(str
));
271 puts ("### No HW ID - assuming VOH405");
276 if (getenv_r("bd_type", str
, sizeof(str
)) != -1) {
277 printf(" (%s)", str
);
279 puts(" (Missing bd_type!)");
285 * Disable sleep mode in LXT971
292 /* ------------------------------------------------------------------------- */
294 long int initdram (int board_type
)
298 mtdcr(memcfga
, mem_mb0cf
);
299 val
= mfdcr(memcfgd
);
302 printf("\nmb0cf=%x\n", val
); /* test-only */
303 printf("strap=%x\n", mfdcr(strap
)); /* test-only */
306 return (4*1024*1024 << ((val
& 0x000e0000) >> 17));
309 /* ------------------------------------------------------------------------- */
313 /* TODO: XXX XXX XXX */
314 printf ("test: 16 MB - ok\n");
319 /* ------------------------------------------------------------------------- */
321 #ifdef CONFIG_IDE_RESET
322 void ide_set_reset(int on
)
324 volatile unsigned short *fpga_mode
=
325 (unsigned short *)((ulong
)CFG_FPGA_BASE_ADDR
+ CFG_FPGA_CTRL
);
328 * Assert or deassert CompactFlash Reset Pin
330 if (on
) { /* assert RESET */
331 *fpga_mode
&= ~(CFG_FPGA_CTRL_CF_RESET
);
332 } else { /* release RESET */
333 *fpga_mode
|= CFG_FPGA_CTRL_CF_RESET
;
336 #endif /* CONFIG_IDE_RESET */