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git.ipfire.org Git - people/ms/u-boot.git/blob - board/esd/vom405/vom405.c
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR
;
32 extern void lxt971_no_sleep(void);
34 int board_early_init_f (void)
37 * IRQ 0-15 405GP internally generated; active high; level sensitive
38 * IRQ 16 405GP internally generated; active low; level sensitive
40 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
41 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
42 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
43 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
44 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
45 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
46 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
48 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
49 mtdcr(uicer
, 0x00000000); /* disable all ints */
50 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
51 mtdcr(uicpr
, 0xFFFFFF80); /* set int polarities */
52 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
53 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority*/
54 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
57 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
59 mtebc (EBC0_CFG
, 0xa8400000); /* ebc always driven */
62 * Reset CPLD via GPIO12 (CS3) pin
64 out_be32((void *)GPIO0_OR
,
65 in_be32((void *)GPIO0_OR
) & ~(0x80000000 >> 12));
66 udelay(1000); /* wait 1ms */
67 out_be32((void *)GPIO0_OR
,
68 in_be32((void *)GPIO0_OR
) | (0x80000000 >> 12));
69 udelay(1000); /* wait 1ms */
74 int misc_init_r (void)
76 /* adjust flash start and offset */
77 gd
->bd
->bi_flashstart
= 0 - gd
->bd
->bi_flashsize
;
78 gd
->bd
->bi_flashoffset
= 0;
84 * Check Board Identity:
89 int i
= getenv_r ("serial#", str
, sizeof(str
));
92 u8
*led_reg
= (u8
*)(CAN_BA
+ 0x1000);
97 puts ("### No HW ID - assuming VOM405");
102 printf(" (PLD-Version=%02d)\n", in_8(led_reg
));
107 for (flashcnt
= 0; flashcnt
< 3; flashcnt
++) {
108 out_8(led_reg
, 0x40); /* LED_B..D off */
109 for (delay
= 0; delay
< 100; delay
++)
111 out_8(led_reg
, 0x47); /* LED_B..D on */
112 for (delay
= 0; delay
< 50; delay
++)
115 out_8(led_reg
, 0x40);
122 #ifdef CONFIG_LXT971_NO_SLEEP
125 * Disable sleep mode in LXT971