board/etin/debris/debris.c

   1 /*
   2  * (C) Copyright 2000
   3  * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mpc824x.h>
  10 #include <net.h>
  11 #include <pci.h>
  12 #include <i2c.h>
  13 #include <netdev.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 int checkboard (void)
  18 {
  19         /*TODO: Check processor type */
  20
  21         puts (  "Board: Debris "
  22 #ifdef CONFIG_MPC8240
  23                 "8240"
  24 #endif
  25 #ifdef CONFIG_MPC8245
  26                 "8245"
  27 #endif
  28                 " ##Test not implemented yet##\n");
  29         return 0;
  30 }
  31
  32 #if 0   /* NOT USED */
  33 int checkflash (void)
  34 {
  35         /* TODO: XXX XXX XXX */
  36         printf ("## Test not implemented yet ##\n");
  37
  38         return (0);
  39 }
  40 #endif
  41
  42 phys_size_t initdram (int board_type)
  43 {
  44         int m, row, col, bank, i;
  45         unsigned long start, end;
  46         uint32_t mccr1;
  47         uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
  48         uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
  49         uint8_t mber = 0;
  50
  51         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  52
  53         if (i2c_reg_read (0x50, 2) != 0x04) return 0;   /* Memory type */
  54         m = i2c_reg_read (0x50, 5);     /* # of physical banks */
  55         row = i2c_reg_read (0x50, 3);   /* # of rows */
  56         col = i2c_reg_read (0x50, 4);   /* # of columns */
  57         bank = i2c_reg_read (0x50, 17); /* # of logical banks */
  58
  59         CONFIG_READ_WORD(MCCR1, mccr1);
  60         mccr1 &= 0xffff0000;
  61
  62         start = CONFIG_SYS_SDRAM_BASE;
  63         end = start + (1 << (col + row + 3) ) * bank - 1;
  64
  65         for (i = 0; i < m; i++) {
  66                 mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
  67                 if (i < 4) {
  68                         msar1  |= ((start >> 20) & 0xff) << i * 8;
  69                         emsar1 |= ((start >> 28) & 0xff) << i * 8;
  70                         mear1  |= ((end >> 20) & 0xff) << i * 8;
  71                         emear1 |= ((end >> 28) & 0xff) << i * 8;
  72                 } else {
  73                         msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
  74                         emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
  75                         mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
  76                         emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
  77                 }
  78                 mber |= 1 << i;
  79                 start += (1 << (col + row + 3) ) * bank;
  80                 end += (1 << (col + row + 3) ) * bank;
  81         }
  82         for (; i < 8; i++) {
  83                 if (i < 4) {
  84                         msar1  |= 0xff << i * 8;
  85                         emsar1 |= 0x30 << i * 8;
  86                         mear1  |= 0xff << i * 8;
  87                         emear1 |= 0x30 << i * 8;
  88                 } else {
  89                         msar2  |= 0xff << (i-4) * 8;
  90                         emsar2 |= 0x30 << (i-4) * 8;
  91                         mear2  |= 0xff << (i-4) * 8;
  92                         emear2 |= 0x30 << (i-4) * 8;
  93                 }
  94         }
  95
  96         CONFIG_WRITE_WORD(MCCR1, mccr1);
  97         CONFIG_WRITE_WORD(MSAR1, msar1);
  98         CONFIG_WRITE_WORD(EMSAR1, emsar1);
  99         CONFIG_WRITE_WORD(MEAR1, mear1);
 100         CONFIG_WRITE_WORD(EMEAR1, emear1);
 101         CONFIG_WRITE_WORD(MSAR2, msar2);
 102         CONFIG_WRITE_WORD(EMSAR2, emsar2);
 103         CONFIG_WRITE_WORD(MEAR2, mear2);
 104         CONFIG_WRITE_WORD(EMEAR2, emear2);
 105         CONFIG_WRITE_BYTE(MBER, mber);
 106
 107         return (1 << (col + row + 3) ) * bank * m;
 108 }
 109
 110 /*
 111  * Initialize PCI Devices, report devices found.
 112  */
 113 #ifndef CONFIG_PCI_PNP
 114 static struct pci_config_table pci_debris_config_table[] = {
 115         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
 116           pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 117                                        PCI_ENET0_MEMADDR,
 118                                        PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
 119         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
 120           pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
 121                                        PCI_ENET1_MEMADDR,
 122                                        PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
 123         { }
 124 };
 125 #endif
 126
 127 struct pci_controller hose = {
 128 #ifndef CONFIG_PCI_PNP
 129         config_table: pci_debris_config_table,
 130 #endif
 131 };
 132
 133 void pci_init_board(void)
 134 {
 135         pci_mpc824x_init(&hose);
 136 }
 137
 138 void *nvram_read(void *dest, const long src, size_t count)
 139 {
 140         volatile uchar *d = (volatile uchar*) dest;
 141         volatile uchar *s = (volatile uchar*) src;
 142         while(count--) {
 143                 *d++ = *s++;
 144                 asm volatile("sync");
 145         }
 146         return dest;
 147 }
 148
 149 void nvram_write(long dest, const void *src, size_t count)
 150 {
 151         volatile uchar *d = (volatile uchar*)dest;
 152         volatile uchar *s = (volatile uchar*)src;
 153         while(count--) {
 154                 *d++ = *s++;
 155                 asm volatile("sync");
 156         }
 157 }
 158
 159 int misc_init_r(void)
 160 {
 161         uchar ethaddr[6];
 162
 163         if (eth_getenv_enetaddr("ethaddr", ethaddr))
 164                 /* Write ethernet addr in NVRAM for VxWorks */
 165                 nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
 166                                 ethaddr, 6);
 167
 168         return 0;
 169 }
 170
 171 int board_eth_init(bd_t *bis)
 172 {
 173         return pci_eth_init(bis);
 174 }