board/etin/debris/debris.c

   1 /*
   2  * (C) Copyright 2000
   3  * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc824x.h>
  26 #include <pci.h>
  27 #include <i2c.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int checkboard (void)
  32 {
  33         /*TODO: Check processor type */
  34
  35         puts (  "Board: Debris "
  36 #ifdef CONFIG_MPC8240
  37                 "8240"
  38 #endif
  39 #ifdef CONFIG_MPC8245
  40                 "8245"
  41 #endif
  42                 " ##Test not implemented yet##\n");
  43         return 0;
  44 }
  45
  46 #if 0   /* NOT USED */
  47 int checkflash (void)
  48 {
  49         /* TODO: XXX XXX XXX */
  50         printf ("## Test not implemented yet ##\n");
  51
  52         return (0);
  53 }
  54 #endif
  55
  56 long int initdram (int board_type)
  57 {
  58         int m, row, col, bank, i;
  59         unsigned long start, end;
  60         uint32_t mccr1;
  61         uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
  62         uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
  63         uint8_t mber = 0;
  64
  65         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
  66
  67         if (i2c_reg_read (0x50, 2) != 0x04) return 0;   /* Memory type */
  68         m = i2c_reg_read (0x50, 5);     /* # of physical banks */
  69         row = i2c_reg_read (0x50, 3);   /* # of rows */
  70         col = i2c_reg_read (0x50, 4);   /* # of columns */
  71         bank = i2c_reg_read (0x50, 17); /* # of logical banks */
  72
  73         CONFIG_READ_WORD(MCCR1, mccr1);
  74         mccr1 &= 0xffff0000;
  75
  76         start = CFG_SDRAM_BASE;
  77         end = start + (1 << (col + row + 3) ) * bank - 1;
  78
  79         for (i = 0; i < m; i++) {
  80                 mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
  81                 if (i < 4) {
  82                         msar1  |= ((start >> 20) & 0xff) << i * 8;
  83                         emsar1 |= ((start >> 28) & 0xff) << i * 8;
  84                         mear1  |= ((end >> 20) & 0xff) << i * 8;
  85                         emear1 |= ((end >> 28) & 0xff) << i * 8;
  86                 } else {
  87                         msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
  88                         emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
  89                         mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
  90                         emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
  91                 }
  92                 mber |= 1 << i;
  93                 start += (1 << (col + row + 3) ) * bank;
  94                 end += (1 << (col + row + 3) ) * bank;
  95         }
  96         for (; i < 8; i++) {
  97                 if (i < 4) {
  98                         msar1  |= 0xff << i * 8;
  99                         emsar1 |= 0x30 << i * 8;
 100                         mear1  |= 0xff << i * 8;
 101                         emear1 |= 0x30 << i * 8;
 102                 } else {
 103                         msar2  |= 0xff << (i-4) * 8;
 104                         emsar2 |= 0x30 << (i-4) * 8;
 105                         mear2  |= 0xff << (i-4) * 8;
 106                         emear2 |= 0x30 << (i-4) * 8;
 107                 }
 108         }
 109
 110         CONFIG_WRITE_WORD(MCCR1, mccr1);
 111         CONFIG_WRITE_WORD(MSAR1, msar1);
 112         CONFIG_WRITE_WORD(EMSAR1, emsar1);
 113         CONFIG_WRITE_WORD(MEAR1, mear1);
 114         CONFIG_WRITE_WORD(EMEAR1, emear1);
 115         CONFIG_WRITE_WORD(MSAR2, msar2);
 116         CONFIG_WRITE_WORD(EMSAR2, emsar2);
 117         CONFIG_WRITE_WORD(MEAR2, mear2);
 118         CONFIG_WRITE_WORD(EMEAR2, emear2);
 119         CONFIG_WRITE_BYTE(MBER, mber);
 120
 121         return (1 << (col + row + 3) ) * bank * m;
 122 }
 123
 124 /*
 125  * Initialize PCI Devices, report devices found.
 126  */
 127 #ifndef CONFIG_PCI_PNP
 128 static struct pci_config_table pci_debris_config_table[] = {
 129         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
 130           pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 131                                        PCI_ENET0_MEMADDR,
 132                                        PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
 133         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
 134           pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
 135                                        PCI_ENET1_MEMADDR,
 136                                        PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
 137         { }
 138 };
 139 #endif
 140
 141 struct pci_controller hose = {
 142 #ifndef CONFIG_PCI_PNP
 143         config_table: pci_debris_config_table,
 144 #endif
 145 };
 146
 147 void pci_init_board(void)
 148 {
 149         pci_mpc824x_init(&hose);
 150 }
 151
 152 void *nvram_read(void *dest, const long src, size_t count)
 153 {
 154         volatile uchar *d = (volatile uchar*) dest;
 155         volatile uchar *s = (volatile uchar*) src;
 156         while(count--) {
 157                 *d++ = *s++;
 158                 asm volatile("sync");
 159         }
 160         return dest;
 161 }
 162
 163 void nvram_write(long dest, const void *src, size_t count)
 164 {
 165         volatile uchar *d = (volatile uchar*)dest;
 166         volatile uchar *s = (volatile uchar*)src;
 167         while(count--) {
 168                 *d++ = *s++;
 169                 asm volatile("sync");
 170         }
 171 }
 172
 173 int misc_init_r(void)
 174 {
 175         /* Write ethernet addr in NVRAM for VxWorks */
 176         nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
 177                         (char*)&gd->bd->bi_enetaddr[0], 6);
 178         return 0;
 179 }