3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 * mpsc.c - driver for console over the MPSC.
14 #include <asm/cache.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 int (*mpsc_putchar
)(char ch
) = mpsc_putchar_early
;
23 static volatile unsigned int *rx_desc_base
=NULL
;
24 static unsigned int rx_desc_index
=0;
25 static volatile unsigned int *tx_desc_base
=NULL
;
26 static unsigned int tx_desc_index
=0;
28 /* local function declarations */
29 static int galmpsc_connect(int channel
, int connect
);
30 static int galmpsc_route_serial(int channel
, int connect
);
31 static int galmpsc_route_rx_clock(int channel
, int brg
);
32 static int galmpsc_route_tx_clock(int channel
, int brg
);
33 static int galmpsc_write_config_regs(int mpsc
, int mode
);
34 static int galmpsc_config_channel_regs(int mpsc
);
35 static int galmpsc_set_char_length(int mpsc
, int value
);
36 static int galmpsc_set_stop_bit_length(int mpsc
, int value
);
37 static int galmpsc_set_parity(int mpsc
, int value
);
38 static int galmpsc_enter_hunt(int mpsc
);
39 static int galmpsc_set_brkcnt(int mpsc
, int value
);
40 static int galmpsc_set_tcschar(int mpsc
, int value
);
41 static int galmpsc_set_snoop(int mpsc
, int value
);
42 static int galmpsc_shutdown(int mpsc
);
44 static int galsdma_set_RFT(int channel
);
45 static int galsdma_set_SFM(int channel
);
46 static int galsdma_set_rxle(int channel
);
47 static int galsdma_set_txle(int channel
);
48 static int galsdma_set_burstsize(int channel
, unsigned int value
);
49 static int galsdma_set_RC(int channel
, unsigned int value
);
51 static int galbrg_set_CDV(int channel
, int value
);
52 static int galbrg_enable(int channel
);
53 static int galbrg_disable(int channel
);
54 static int galbrg_set_clksrc(int channel
, int value
);
55 static int galbrg_set_CUV(int channel
, int value
);
57 static void galsdma_enable_rx(void);
59 /* static int galbrg_reset(int channel); */
61 #define SOFTWARE_CACHE_MANAGEMENT
63 #ifdef SOFTWARE_CACHE_MANAGEMENT
64 #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
65 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
66 #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
68 #define FLUSH_DCACHE(a,b)
69 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
70 #define INVALIDATE_DCACHE(a,b)
74 /* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
75 #define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->arch.mirror_hack[0]))
77 #define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
78 #define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
80 #define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);}
81 #define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i])
83 /* make sure this isn't bigger than 16 long words (u-boot.h) */
84 struct _tag_mirror_hack
{
85 unsigned GALMPSC_PROTOCONF_REG_M
[2]; /* 8008 */
86 unsigned GALMPSC_CHANNELREG_1_M
[2]; /* 800c */
87 unsigned GALMPSC_CHANNELREG_2_M
[2]; /* 8010 */
88 unsigned GALBRG_0_CONFREG_M
[2]; /* b200 */
90 unsigned GALMPSC_ROUTING_REGISTER_M
; /* b400 */
91 unsigned GALMPSC_RxC_ROUTE_M
; /* b404 */
92 unsigned GALMPSC_TxC_ROUTE_M
; /* b408 */
94 unsigned int baudrate
; /* current baudrate, for tsc delay calc */
97 /* static struct _tag_mirror_hack *mh = NULL; */
99 /* special function for running out of flash. doesn't modify any
100 * global variables [josh] */
102 mpsc_putchar_early(char ch
)
105 int temp
=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
);
106 galmpsc_set_tcschar(mpsc
,ch
);
107 GT_REG_WRITE(GALMPSC_CHANNELREG_2
+(mpsc
*GALMPSC_REG_GAP
), temp
|0x200);
109 #define MAGIC_FACTOR (10*1000000)
111 udelay(MAGIC_FACTOR
/ MIRROR_HACK
->baudrate
);
115 /* This is used after relocation, see serial.c and mpsc_init2 */
117 mpsc_putchar_sdma(char ch
)
119 volatile unsigned int *p
;
123 /* align the descriptor */
125 memset((void *)p
, 0, 8 * sizeof(unsigned int));
127 /* fill one 64 bit buffer */
128 /* word swap, pad with 0 */
130 p
[5] = (unsigned int)ch
; /* x */
132 /* CHANGED completely according to GT64260A dox - NTL */
133 p
[0] = 0x00010001; /* 0 */
134 p
[1] = DESC_OWNER
| DESC_FIRST
| DESC_LAST
; /* 4 */
136 p
[3] = (unsigned int)&p
[4]; /* c */
139 p
[9] = DESC_FIRST
| DESC_LAST
;
140 p
[10] = (unsigned int)&p
[0];
141 p
[11] = (unsigned int)&p
[12];
144 FLUSH_DCACHE(&p
[0], &p
[8]);
146 GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR
+(CHANNEL
*GALSDMA_REG_DIFF
),
147 (unsigned int)&p
[0]);
148 GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR
+(CHANNEL
*GALSDMA_REG_DIFF
),
149 (unsigned int)&p
[0]);
151 temp
= GTREGREAD(GALSDMA_0_COM_REG
+(CHANNEL
*GALSDMA_REG_DIFF
));
152 temp
|= (TX_DEMAND
| TX_STOP
);
153 GT_REG_WRITE(GALSDMA_0_COM_REG
+(CHANNEL
*GALSDMA_REG_DIFF
), temp
);
155 INVALIDATE_DCACHE(&p
[1], &p
[2]);
157 while(p
[1] & DESC_OWNER
) {
159 INVALIDATE_DCACHE(&p
[1], &p
[2]);
165 char mpsc_getchar (void)
167 static unsigned int done
= 0;
169 unsigned int len
= 0, idx
= 0, temp
;
171 volatile unsigned int *p
;
175 p
= &rx_desc_base
[rx_desc_index
* 8];
177 INVALIDATE_DCACHE (&p
[0], &p
[1]);
178 /* Wait for character */
179 while (p
[1] & DESC_OWNER
) {
181 INVALIDATE_DCACHE (&p
[0], &p
[1]);
184 /* Handle error case */
185 if (p
[1] & (1 << 15)) {
186 printf ("oops, error: %08x\n", p
[1]);
188 temp
= GTREGREAD_MIRROR (GALMPSC_CHANNELREG_2
,
189 CHANNEL
, GALMPSC_REG_GAP
);
191 GT_REG_WRITE_MIRROR (GALMPSC_CHANNELREG_2
, CHANNEL
,
192 GALMPSC_REG_GAP
, temp
);
194 /* Can't poll on abort bit, so we just wait. */
197 galsdma_enable_rx ();
200 /* Number of bytes left in this descriptor */
213 INVALIDATE_DCACHE (&p
[idx
], &p
[idx
+ 1]);
219 /* this descriptor has more bytes still
220 * shift down the char we just read, and leave the
221 * buffer in place for the next time around
223 p
[idx
] = p
[idx
] >> 8;
224 FLUSH_DCACHE (&p
[idx
], &p
[idx
+ 1]);
228 /* nothing left in this descriptor.
231 p
[1] = DESC_OWNER
| DESC_FIRST
| DESC_LAST
;
233 FLUSH_DCACHE (&p
[0], &p
[1]);
234 /* Next descriptor */
235 rx_desc_index
= (rx_desc_index
+ 1) % RX_DESC
;
238 } while (len
== 0); /* galileo bug.. len might be zero */
246 volatile unsigned int *p
= &rx_desc_base
[rx_desc_index
*8];
248 INVALIDATE_DCACHE(&p
[1], &p
[2]);
250 if (p
[1] & DESC_OWNER
) return 0;
257 memset(MIRROR_HACK
, 0, sizeof(struct _tag_mirror_hack
));
258 MIRROR_HACK
->GALMPSC_ROUTING_REGISTER_M
=0x3fffffff;
261 galbrg_set_baudrate(CHANNEL
, baud
);
262 #if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
263 galbrg_set_clksrc(CHANNEL
,0x8); /* connect TCLK -> BRG */
265 galbrg_set_clksrc(CHANNEL
,0);
267 galbrg_set_CUV(CHANNEL
, 0);
268 galbrg_enable(CHANNEL
);
270 /* Set up clock routing */
271 galmpsc_connect(CHANNEL
, GALMPSC_CONNECT
);
272 galmpsc_route_serial(CHANNEL
, GALMPSC_CONNECT
);
273 galmpsc_route_rx_clock(CHANNEL
, CHANNEL
);
274 galmpsc_route_tx_clock(CHANNEL
, CHANNEL
);
276 /* reset MPSC state */
277 galmpsc_shutdown(CHANNEL
);
280 galsdma_set_burstsize(CHANNEL
, L1_CACHE_BYTES
/8); /* in 64 bit words (8 bytes) */
281 galsdma_set_txle(CHANNEL
);
282 galsdma_set_rxle(CHANNEL
);
283 galsdma_set_RC(CHANNEL
, 0xf);
284 galsdma_set_SFM(CHANNEL
);
285 galsdma_set_RFT(CHANNEL
);
288 galmpsc_write_config_regs(CHANNEL
, GALMPSC_UART
);
289 galmpsc_config_channel_regs(CHANNEL
);
290 galmpsc_set_char_length(CHANNEL
, GALMPSC_CHAR_LENGTH_8
); /* 8 */
291 galmpsc_set_parity(CHANNEL
, GALMPSC_PARITY_NONE
); /* N */
292 galmpsc_set_stop_bit_length(CHANNEL
, GALMPSC_STOP_BITS_1
); /* 1 */
294 /* COMM_MPSC CONFIG */
295 #ifdef SOFTWARE_CACHE_MANAGEMENT
296 galmpsc_set_snoop(CHANNEL
, 0); /* disable snoop */
298 galmpsc_set_snoop(CHANNEL
, 1); /* enable snoop */
309 mpsc_putchar
= mpsc_putchar_sdma
;
312 rx_desc_base
= (unsigned int *)malloc(((RX_DESC
+1)*8) *
313 sizeof(unsigned int));
315 /* align descriptors */
316 rx_desc_base
= (unsigned int *)
317 (((unsigned int)rx_desc_base
+32) & 0xFFFFFFF0);
321 memset((void *)rx_desc_base
, 0, (RX_DESC
*8)*sizeof(unsigned int));
323 for (i
= 0; i
< RX_DESC
; i
++) {
324 rx_desc_base
[i
*8 + 3] = (unsigned int)&rx_desc_base
[i
*8 + 4]; /* Buffer */
325 rx_desc_base
[i
*8 + 2] = (unsigned int)&rx_desc_base
[(i
+1)*8]; /* Next descriptor */
326 rx_desc_base
[i
*8 + 1] = DESC_OWNER
| DESC_FIRST
| DESC_LAST
; /* Command & control */
327 rx_desc_base
[i
*8] = 0x00100000;
329 rx_desc_base
[(i
-1)*8 + 2] = (unsigned int)&rx_desc_base
[0];
331 FLUSH_DCACHE(&rx_desc_base
[0], &rx_desc_base
[RX_DESC
*8]);
332 GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR
+(CHANNEL
*GALSDMA_REG_DIFF
),
333 (unsigned int)&rx_desc_base
[0]);
336 tx_desc_base
= (unsigned int *)malloc(((TX_DESC
+1)*8) *
337 sizeof(unsigned int));
339 /* align descriptors */
340 tx_desc_base
= (unsigned int *)
341 (((unsigned int)tx_desc_base
+32) & 0xFFFFFFF0);
345 memset((void *)tx_desc_base
, 0, (TX_DESC
*8)*sizeof(unsigned int));
347 for (i
= 0; i
< TX_DESC
; i
++) {
348 tx_desc_base
[i
*8 + 5] = (unsigned int)0x23232323;
349 tx_desc_base
[i
*8 + 4] = (unsigned int)0x23232323;
350 tx_desc_base
[i
*8 + 3] = (unsigned int)&tx_desc_base
[i
*8 + 4];
351 tx_desc_base
[i
*8 + 2] = (unsigned int)&tx_desc_base
[(i
+1)*8];
352 tx_desc_base
[i
*8 + 1] = DESC_OWNER
| DESC_FIRST
| DESC_LAST
;
354 /* set sbytecnt and shadow byte cnt to 1 */
355 tx_desc_base
[i
*8] = 0x00010001;
357 tx_desc_base
[(i
-1)*8 + 2] = (unsigned int)&tx_desc_base
[0];
359 FLUSH_DCACHE(&tx_desc_base
[0], &tx_desc_base
[TX_DESC
*8]);
369 galbrg_set_baudrate(int channel
, int rate
)
373 galbrg_disable(channel
);
375 #if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
377 clock
= (CONFIG_SYS_BUS_CLK
/(16*rate
)) - 1;
379 clock
= (3686400/(16*rate
)) - 1;
382 galbrg_set_CDV(channel
, clock
);
384 galbrg_enable(channel
);
386 MIRROR_HACK
->baudrate
= rate
;
391 /* ------------------------------------------------------------------ */
393 /* Below are all the private functions that no one else needs */
396 galbrg_set_CDV(int channel
, int value
)
400 temp
= GTREGREAD_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
);
402 temp
|= (value
& 0x0000FFFF);
403 GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG
,channel
,GALBRG_REG_GAP
, temp
);
409 galbrg_enable(int channel
)
413 temp
= GTREGREAD_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
);
415 GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
,temp
);
421 galbrg_disable(int channel
)
425 temp
= GTREGREAD_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
);
427 GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG
, channel
, GALBRG_REG_GAP
,temp
);
433 galbrg_set_clksrc(int channel
, int value
)
437 temp
= GTREGREAD_MIRROR(GALBRG_0_CONFREG
,channel
, GALBRG_REG_GAP
);
439 temp
|= (value
<< 18);
440 GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG
,channel
, GALBRG_REG_GAP
,temp
);
446 galbrg_set_CUV(int channel
, int value
)
448 GT_REG_WRITE(GALBRG_0_BTREG
+ (channel
* GALBRG_REG_GAP
), value
);
455 galbrg_reset(int channel
)
459 temp
= GTREGREAD(GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
461 GT_REG_WRITE(GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
468 galsdma_set_RFT(int channel
)
472 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
474 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
480 galsdma_set_SFM(int channel
)
484 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
486 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
492 galsdma_set_rxle(int channel
)
496 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
498 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
504 galsdma_set_txle(int channel
)
508 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
510 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
516 galsdma_set_RC(int channel
, unsigned int value
)
520 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
522 temp
|= (value
<< 2);
523 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
), temp
);
529 galsdma_set_burstsize(int channel
, unsigned int value
)
533 temp
= GTREGREAD(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
));
537 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
),
538 (temp
| (0x3 << 12)));
542 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
),
543 (temp
| (0x2 << 12)));
547 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
),
548 (temp
| (0x1 << 12)));
552 GT_REG_WRITE(GALSDMA_0_CONF_REG
+(channel
*GALSDMA_REG_DIFF
),
553 (temp
| (0x0 << 12)));
565 galmpsc_connect(int channel
, int connect
)
569 temp
= GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER
);
571 if ((channel
== 0) && connect
)
573 else if ((channel
== 1) && connect
)
574 temp
&= ~(0x00000007 << 6);
575 else if ((channel
== 0) && !connect
)
578 temp
|= (0x00000007 << 6);
580 /* Just in case... */
583 GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER
, temp
);
589 galmpsc_route_serial(int channel
, int connect
)
593 temp
= GTREGREAD(GALMPSC_SERIAL_MULTIPLEX
);
595 if ((channel
== 0) && connect
)
597 else if ((channel
== 1) && connect
)
599 else if ((channel
== 0) && !connect
)
604 GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX
,temp
);
610 galmpsc_route_rx_clock(int channel
, int brg
)
614 temp
= GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE
);
621 GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE
,temp
);
627 galmpsc_route_tx_clock(int channel
, int brg
)
631 temp
= GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE
);
638 GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE
,temp
);
644 galmpsc_write_config_regs(int mpsc
, int mode
)
646 if (mode
== GALMPSC_UART
) {
647 /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
648 GT_REG_WRITE(GALMPSC_MCONF_LOW
+ (mpsc
*GALMPSC_REG_GAP
),
651 /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
652 GT_REG_WRITE(GALMPSC_MCONF_HIGH
+(mpsc
*GALMPSC_REG_GAP
),
656 /* 0000 0010 0000 0000 */
659 /* 0000 0011 1111 1000 */
667 galmpsc_config_channel_regs(int mpsc
)
669 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
, 0);
670 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
, 0);
671 GT_REG_WRITE(GALMPSC_CHANNELREG_3
+(mpsc
*GALMPSC_REG_GAP
), 1);
672 GT_REG_WRITE(GALMPSC_CHANNELREG_4
+(mpsc
*GALMPSC_REG_GAP
), 0);
673 GT_REG_WRITE(GALMPSC_CHANNELREG_5
+(mpsc
*GALMPSC_REG_GAP
), 0);
674 GT_REG_WRITE(GALMPSC_CHANNELREG_6
+(mpsc
*GALMPSC_REG_GAP
), 0);
675 GT_REG_WRITE(GALMPSC_CHANNELREG_7
+(mpsc
*GALMPSC_REG_GAP
), 0);
676 GT_REG_WRITE(GALMPSC_CHANNELREG_8
+(mpsc
*GALMPSC_REG_GAP
), 0);
677 GT_REG_WRITE(GALMPSC_CHANNELREG_9
+(mpsc
*GALMPSC_REG_GAP
), 0);
678 GT_REG_WRITE(GALMPSC_CHANNELREG_10
+(mpsc
*GALMPSC_REG_GAP
), 0);
680 galmpsc_set_brkcnt(mpsc
, 0x3);
681 galmpsc_set_tcschar(mpsc
, 0xab);
687 galmpsc_set_brkcnt(int mpsc
, int value
)
691 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
);
693 temp
|= (value
<< 16);
694 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
, temp
);
700 galmpsc_set_tcschar(int mpsc
, int value
)
704 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
);
707 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1
,mpsc
,GALMPSC_REG_GAP
, temp
);
713 galmpsc_set_char_length(int mpsc
, int value
)
717 temp
= GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG
,mpsc
,GALMPSC_REG_GAP
);
719 temp
|= (value
<< 12);
720 GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG
,mpsc
,GALMPSC_REG_GAP
, temp
);
726 galmpsc_set_stop_bit_length(int mpsc
, int value
)
730 temp
= GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG
,mpsc
,GALMPSC_REG_GAP
);
731 temp
|= (value
<< 14);
732 GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG
,mpsc
,GALMPSC_REG_GAP
,temp
);
738 galmpsc_set_parity(int mpsc
, int value
)
742 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
);
745 temp
|= ((value
<< 18) | (value
<< 2));
746 temp
|= ((value
<< 17) | (value
<< 1));
751 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
, temp
);
757 galmpsc_enter_hunt(int mpsc
)
761 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
);
763 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
, temp
);
765 /* Should Poll on Enter Hunt bit, but the register is write-only */
766 /* errata suggests pausing 100 system cycles */
774 galmpsc_shutdown(int mpsc
)
779 /* cause RX abort (clears RX) */
780 temp
= GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
);
781 temp
|= MPSC_RX_ABORT
| MPSC_TX_ABORT
;
782 temp
&= ~MPSC_ENTER_HUNT
;
783 GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2
,mpsc
,GALMPSC_REG_GAP
,temp
);
786 GT_REG_WRITE(GALSDMA_0_COM_REG
+ CHANNEL
* GALSDMA_REG_DIFF
, 0);
787 GT_REG_WRITE(GALSDMA_0_COM_REG
+ CHANNEL
* GALSDMA_REG_DIFF
,
788 SDMA_TX_ABORT
| SDMA_RX_ABORT
);
790 /* shut down the MPSC */
791 GT_REG_WRITE(GALMPSC_MCONF_LOW
, 0);
792 GT_REG_WRITE(GALMPSC_MCONF_HIGH
, 0);
793 GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG
, mpsc
, GALMPSC_REG_GAP
,0);
797 /* shut down the sdma engines. */
798 /* reset config to default */
799 GT_REG_WRITE(GALSDMA_0_CONF_REG
+ CHANNEL
* GALSDMA_REG_DIFF
,
804 /* clear the SDMA current and first TX and RX pointers */
805 GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR
+ CHANNEL
* GALSDMA_REG_DIFF
, 0);
806 GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR
+ CHANNEL
* GALSDMA_REG_DIFF
, 0);
807 GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR
+ CHANNEL
* GALSDMA_REG_DIFF
, 0);
815 galsdma_enable_rx(void)
819 /* Enable RX processing */
820 temp
= GTREGREAD(GALSDMA_0_COM_REG
+(CHANNEL
*GALSDMA_REG_DIFF
));
822 GT_REG_WRITE(GALSDMA_0_COM_REG
+(CHANNEL
*GALSDMA_REG_DIFF
), temp
);
824 galmpsc_enter_hunt(CHANNEL
);
828 galmpsc_set_snoop(int mpsc
, int value
)
830 int reg
= mpsc
? MPSC_1_ADDRESS_CONTROL_LOW
: MPSC_0_ADDRESS_CONTROL_LOW
;
831 int temp
=GTREGREAD(reg
);
833 temp
|= (1<< 6) | (1<<14) | (1<<22) | (1<<30);
835 temp
&= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30));
836 GT_REG_WRITE(reg
, temp
);