3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* sdram_init.c - automatic memory sizing */
28 #include <galileo/memory.h>
29 #include <galileo/pci.h>
30 #include <galileo/gt64260R.h>
49 /* structure to store the relevant information about an sdram bank */
50 typedef struct sdram_info
{
52 uchar registered
, ecc
;
57 int size
; /* detected size, not from I2C but from dram_size() */
61 void dump_dimm_info(struct sdram_info
*d
)
63 static const char *ecc_legend
[]={""," Parity"," ECC"};
64 printf("dimm%s %sDRAM: %dMibytes:\n",
68 printf(" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
69 d
->drb_size
, d
->tpar
, d
->tras_clocks
, d
->burst_len
,
75 memory_map_bank(unsigned int bankNo
,
76 unsigned int bankBase
,
77 unsigned int bankLength
)
81 printf("mapping bank %d at %08x - %08x\n",
82 bankNo
, bankBase
, bankBase
+ bankLength
- 1);
84 printf("unmapping bank %d\n", bankNo
);
88 memoryMapBank(bankNo
, bankBase
, bankLength
);
95 memory_map_bank_pci(unsigned int bankNo
,
96 unsigned int bankBase
,
97 unsigned int bankLength
)
100 for (host
=PCI_HOST0
;host
<=PCI_HOST1
;host
++) {
103 DELAYED_READ_ENABLE
|
104 AGGRESSIVE_PREFETCH
|
105 READ_LINE_AGGRESSIVE_PREFETCH
|
106 READ_MULTI_AGGRESSIVE_PREFETCH
|
110 pciMapMemoryBank(host
, bankNo
, bankBase
, bankLength
);
112 pciSetRegionSnoopMode(host
, bankNo
, PCI_SNOOP_WB
, bankBase
,
115 pciSetRegionFeatures(host
, bankNo
, features
, bankBase
, bankLength
);
121 /* ------------------------------------------------------------------------- */
123 /* much of this code is based on (or is) the code in the pip405 port */
124 /* thanks go to the authors of said port - Josh */
128 * translate ns.ns/10 coding of SPD timing values
129 * into 10 ps unit values
131 static inline unsigned short
132 NS10to10PS(unsigned char spd_byte
)
134 unsigned short ns
, ns10
;
136 /* isolate upper nibble */
137 ns
= (spd_byte
>> 4) & 0x0F;
138 /* isolate lower nibble */
139 ns10
= (spd_byte
& 0x0F);
141 return(ns
*100 + ns10
*10);
145 * translate ns coding of SPD timing values
146 * into 10 ps unit values
148 static inline unsigned short
149 NSto10PS(unsigned char spd_byte
)
151 return(spd_byte
*100);
154 #ifdef CONFIG_ZUMA_V2
156 check_dimm(uchar slot
, sdram_info_t
*info
)
158 /* assume 2 dimms, 2 banks each 256M - we dont have an
159 * dimm i2c so rely on the detection routines later */
161 memset(info
, 0, sizeof(*info
));
164 info
->banks
= 2; /* Detect later */
165 info
->registered
= 0;
166 info
->drb_size
= 32; /* 16 - 256MBit, 32 - 512MBit
167 but doesn't matter, both do same
168 thing in setup_sdram() */
170 info
->tras_clocks
= 5;
173 info
->ecc
= 0; /* Detect later */
174 #endif /* CONFIG_ECC */
178 #else /* ! CONFIG_ZUMA_V2 */
180 /* This code reads the SPD chip on the sdram and populates
181 * the array which is passed in with the relevant information */
183 check_dimm(uchar slot
, sdram_info_t
*info
)
185 DECLARE_GLOBAL_DATA_PTR
;
186 uchar addr
= slot
== 0 ? DIMM0_I2C_ADDR
: DIMM1_I2C_ADDR
;
188 uchar rows
, cols
, sdram_banks
, supp_cal
, width
, cal_val
;
190 uchar trp_clocks
, trcd_clocks
;
195 tmemclk
= 1000000000 / (gd
->bus_clk
/ 100); /* in 10 ps units */
197 #ifdef CONFIG_EVB64260_750CX
199 printf("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
200 printf(" called with slot=%d insetad!\n", slot
);
204 DP(puts("before i2c read\n"));
206 ret
= i2c_read(addr
, 0, 128, data
, 0);
208 DP(puts("after i2c read\n"));
210 /* zero all the values */
211 memset(info
, 0, sizeof(*info
));
214 DP(printf("No DIMM in slot %d [err = %x]\n", slot
, ret
));
218 /* first, do some sanity checks */
219 if (data
[2] != 0x4) {
220 printf("Not SDRAM in slot %d\n", slot
);
224 /* get various information */
227 info
->banks
= data
[5];
228 sdram_banks
= data
[17];
229 width
= data
[13] & 0x7f;
231 DP(printf("sdram_banks: %d, banks: %d\n", sdram_banks
, info
->banks
));
233 /* check if the memory is registered */
234 if (data
[21] & (BIT1
| BIT4
))
235 info
->registered
= 1;
238 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
239 info
->ecc
= (data
[11] & 2) >> 1;
242 /* bit 1 is CL2, bit 2 is CL3 */
243 supp_cal
= (data
[18] & 0x6) >> 1;
245 /* compute the relevant clock values */
246 trp_clocks
= (NSto10PS(data
[27])+(tmemclk
-1)) / tmemclk
;
247 trcd_clocks
= (NSto10PS(data
[29])+(tmemclk
-1)) / tmemclk
;
248 info
->tras_clocks
= (NSto10PS(data
[30])+(tmemclk
-1)) / tmemclk
;
250 DP(printf("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
251 trp_clocks
, trcd_clocks
, info
->tras_clocks
));
253 /* try a CAS latency of 3 first... */
256 if (NS10to10PS(data
[9]) <= tmemclk
)
262 if (NS10to10PS(data
[23]) <= tmemclk
)
266 DP(printf("cal_val = %d\n", cal_val
));
268 /* bummer, did't work... */
270 DP(printf("Couldn't find a good CAS latency\n"));
274 /* get the largest delay -- these values need to all be the same
276 info
->tpar
= cal_val
;
277 if (trp_clocks
> info
->tpar
)
278 info
->tpar
= trp_clocks
;
279 if (trcd_clocks
> info
->tpar
)
280 info
->tpar
= trcd_clocks
;
282 DP(printf("tpar set to: %d\n", info
->tpar
));
284 #ifdef CFG_BROKEN_CL2
285 if (info
->tpar
== 2){
287 DP(printf("tpar fixed-up to: %d\n", info
->tpar
));
290 /* compute the module DRB size */
291 info
->drb_size
= (((1 << (rows
+ cols
)) * sdram_banks
) * width
) / _16M
;
293 DP(printf("drb_size set to: %d\n", info
->drb_size
));
295 /* find the burst len */
296 info
->burst_len
= data
[16] & 0xf;
297 if ((info
->burst_len
& 8) == 8) {
299 } else if ((info
->burst_len
& 4) == 4) {
308 #endif /* ! CONFIG_ZUMA_V2 */
311 setup_sdram_common(sdram_info_t info
[2])
314 int tpar
=2, tras_clocks
=5, registered
=1, ecc
=2;
316 if(!info
[0].banks
&& !info
[1].banks
) return 0;
319 if(info
[0].tpar
>tpar
) tpar
=info
[0].tpar
;
320 if(info
[0].tras_clocks
>tras_clocks
) tras_clocks
=info
[0].tras_clocks
;
321 if(!info
[0].registered
) registered
=0;
322 if(info
[0].ecc
!=2) ecc
=0;
326 if(info
[1].tpar
>tpar
) tpar
=info
[1].tpar
;
327 if(info
[1].tras_clocks
>tras_clocks
) tras_clocks
=info
[1].tras_clocks
;
328 if(!info
[1].registered
) registered
=0;
329 if(info
[1].ecc
!=2) ecc
=0;
332 /* SDRAM configuration */
333 tmp
= GTREGREAD(SDRAM_CONFIGURATION
);
335 /* Turn on physical interleave if both DIMMs
336 * have even numbers of banks. */
337 if( (info
[0].banks
== 0 || info
[0].banks
== 2) &&
338 (info
[1].banks
== 0 || info
[1].banks
== 2) ) {
339 /* physical interleave on */
342 /* physical interleave off */
346 tmp
|= (registered
<< 17);
348 /* Use buffer 1 to return read data to the CPU
352 GT_REG_WRITE(SDRAM_CONFIGURATION
, tmp
);
353 DP(printf("SDRAM config: %08x\n",
354 GTREGREAD(SDRAM_CONFIGURATION
)));
357 tmp
= (((tpar
== 3) ? 2 : 1) |
358 (((tpar
== 3) ? 2 : 1) << 2) |
359 (((tpar
== 3) ? 2 : 1) << 4) |
364 if (ecc
== 2) tmp
|= 1<<13;
365 #endif /* CONFIG_ECC */
367 GT_REG_WRITE(SDRAM_TIMING
, tmp
);
368 DP(printf("SDRAM timing: %08x (%d,%d,%d,%d)\n",
369 GTREGREAD(SDRAM_TIMING
), tpar
,tpar
,tpar
,tras_clocks
));
371 /* SDRAM address decode register */
372 /* program this with the default value */
373 GT_REG_WRITE(SDRAM_ADDRESS_DECODE
, 0x2);
374 DP(printf("SDRAM decode: %08x\n",
375 GTREGREAD(SDRAM_ADDRESS_DECODE
)));
380 /* sets up the GT properly with information passed in */
382 setup_sdram(sdram_info_t
*info
)
388 /* sanity checking */
389 if (! info
->banks
) return 0;
391 /* ---------------------------- */
392 /* Program the GT with the discovered data */
394 /* bank parameters */
395 tmp
= (0xf<<16); /* leave all virt bank pages open */
397 DP(printf("drb_size: %d\n", info
->drb_size
));
398 switch (info
->drb_size
) {
411 printf("Error in dram size calculation\n");
415 /* SDRAM bank parameters */
416 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
417 GT_REG_WRITE(SDRAM_BANK0PARAMETERS
+ (info
->slot
* 0x8), tmp
);
418 GT_REG_WRITE(SDRAM_BANK1PARAMETERS
+ (info
->slot
* 0x8), tmp
);
419 DP(printf("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info
->slot
, info
->slot
*2, (info
->slot
*2)+1, tmp
));
421 /* set the SDRAM configuration for each bank */
422 for (i
= info
->slot
* 2; i
< ((info
->slot
* 2) + info
->banks
); i
++) {
423 DP(printf("*** Running a MRS cycle for bank %d ***\n", i
));
426 memory_map_bank(i
, 0, GB
/4);
429 GT_REG_WRITE(SDRAM_OPERATION_MODE
, 0x3);
430 check
= GTREGREAD(SDRAM_OPERATION_MODE
);
435 /* wait for the command to complete */
436 while ((GTREGREAD(SDRAM_OPERATION_MODE
) & (1 << 31)) == 0)
439 /* switch back to normal operation mode */
440 GT_REG_WRITE(SDRAM_OPERATION_MODE
, 0);
441 check
= GTREGREAD(SDRAM_OPERATION_MODE
);
444 memory_map_bank(i
, 0, 0);
445 DP(printf("*** MRS cycle for bank %d done ***\n", i
));
452 * Check memory range for valid RAM. A simple memory test determines
453 * the actually available RAM size between addresses `base' and
454 * `base + maxsize'. Some (not all) hardware errors are detected:
455 * - short between address lines
456 * - short between data lines
459 dram_size(long int *base
, long int maxsize
)
461 volatile long int *addr
, *b
=base
;
462 long int cnt
, val
, save1
, save2
;
464 #define STARTVAL (1<<20) /* start test at 1M */
465 for (cnt
= STARTVAL
/sizeof(long); cnt
< maxsize
/sizeof(long); cnt
<<= 1) {
466 addr
= base
+ cnt
; /* pointer arith! */
468 save1
=*addr
; /* save contents of addr */
469 save2
=*b
; /* save contents of base */
471 *addr
=cnt
; /* write cnt to addr */
472 *b
=0; /* put null at base */
474 /* check at base address */
476 *addr
=save1
; /* restore *addr */
477 *b
=save2
; /* restore *b */
480 val
= *addr
; /* read *addr */
486 /* fix boundary condition.. STARTVAL means zero */
487 if(cnt
==STARTVAL
/sizeof(long)) cnt
=0;
488 return (cnt
* sizeof(long));
494 /* ------------------------------------------------------------------------- */
496 /* U-Boot interface function to SDRAM init - this is where all the
497 * controlling logic happens */
499 initdram(int board_type
)
501 ulong checkbank
[4] = { [0 ... 3] = 0 };
505 sdram_info_t dimm_info
[2];
508 /* first, use the SPD to get info about the SDRAM */
510 /* check the NHR bit and skip mem init if it's already done */
511 nhr
= get_hid0() & (1 << 16);
514 printf("Skipping SDRAM setup due to NHR bit being set\n");
517 check_dimm(0, &dimm_info
[0]);
520 #ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
521 check_dimm(1, &dimm_info
[1]);
522 #else /* CONFIG_EVB64260_750CX */
523 memset(&dimm_info
[1], 0, sizeof(sdram_info_t
));
526 /* unmap all banks */
527 memory_map_bank(0, 0, 0);
528 memory_map_bank(1, 0, 0);
529 memory_map_bank(2, 0, 0);
530 memory_map_bank(3, 0, 0);
532 /* Now, program the GT with the correct values */
533 if (setup_sdram_common(dimm_info
)) {
534 printf("Setup common failed.\n");
537 if (setup_sdram(&dimm_info
[0])) {
538 printf("Setup for DIMM1 failed.\n");
541 if (setup_sdram(&dimm_info
[1])) {
542 printf("Setup for DIMM2 failed.\n");
545 /* set the NHR bit */
546 set_hid0(get_hid0() | (1 << 16));
548 /* next, size the SDRAM banks */
551 if (dimm_info
[0].banks
> 0) checkbank
[0] = 1;
552 if (dimm_info
[0].banks
> 1) checkbank
[1] = 1;
553 if (dimm_info
[0].banks
> 2)
554 printf("Error, SPD claims DIMM1 has >2 banks\n");
556 if (dimm_info
[1].banks
> 0) checkbank
[2] = 1;
557 if (dimm_info
[1].banks
> 1) checkbank
[3] = 1;
558 if (dimm_info
[1].banks
> 2)
559 printf("Error, SPD claims DIMM2 has >2 banks\n");
561 /* Generic dram sizer: works even if we don't have i2c DIMMs,
562 * as long as the timing settings are more or less correct */
565 * pass 1: size all the banks, using first bat (0-256M)
566 * limitation: we only support 256M per bank due to
567 * us only having 1 BAT for all DRAM
569 for (bank_no
= 0; bank_no
< CFG_DRAM_BANKS
; bank_no
++) {
570 /* skip over banks that are not populated */
571 if (! checkbank
[bank_no
])
574 DP(printf("checking bank %d\n", bank_no
));
576 memory_map_bank(bank_no
, 0, GB
/4);
577 checkbank
[bank_no
] = dram_size(NULL
, GB
/4);
578 memory_map_bank(bank_no
, 0, 0);
580 DP(printf("bank %d %08lx\n", bank_no
, checkbank
[bank_no
]));
584 * pass 2: contiguously map each bank into physical address
587 dimm_info
[0].banks
=dimm_info
[1].banks
=0;
588 for (bank_no
= 0; bank_no
< CFG_DRAM_BANKS
; bank_no
++) {
589 if(!checkbank
[bank_no
]) continue;
591 dimm_info
[bank_no
/2].banks
++;
592 dimm_info
[bank_no
/2].size
+=checkbank
[bank_no
];
594 memory_map_bank(bank_no
, total
, checkbank
[bank_no
]);
596 memory_map_bank_pci(bank_no
, total
, checkbank
[bank_no
]);
598 total
+= checkbank
[bank_no
];
602 #ifdef CONFIG_ZUMA_V2
604 * We always enable ECC when bank 2 and 3 are unpopulated
605 * If we 2 or 3 are populated, we CAN'T support ECC.
606 * (Zuma boards only support ECC in banks 0 and 1; assume that
607 * in that configuration, ECC chips are mounted, even for stacked
610 if (checkbank
[2]==0 && checkbank
[3]==0) {
612 GT_REG_WRITE(SDRAM_TIMING
, GTREGREAD(SDRAM_TIMING
) | (1 << 13));
613 /* TODO: do we have to run MRS cycles again? */
615 #endif /* CONFIG_ZUMA_V2 */
617 if (GTREGREAD(SDRAM_TIMING
) & (1 << 13)) {
620 #endif /* CONFIG_ECC */
623 dump_dimm_info(&dimm_info
[0]);
624 dump_dimm_info(&dimm_info
[1]);
626 /* TODO: return at MOST 256M? */
627 /* return total > GB/4 ? GB/4 : total; */