board/exbitgen/init.S

   1 /*----------------------------------------------------------------------+
   2  *
   3  *       This source code has been made available to you by IBM on an AS-IS
   4  *       basis.  Anyone receiving this source is licensed under IBM
   5  *       copyrights to use it in any way he or she deems fit, including
   6  *       copying it, modifying it, compiling it, and redistributing it either
   7  *       with or without modifications.  No license under IBM patents or
   8  *       patent applications is to be implied by the copyright license.
   9  *
  10  *       Any user of this software should understand that IBM cannot provide
  11  *       technical support for this software and will not be responsible for
  12  *       any consequences resulting from the use of this software.
  13  *
  14  *       Any person who transfers this source code or any derivative work
  15  *       must include the IBM copyright notice, this paragraph, and the
  16  *       preceding two paragraphs in the transferred software.
  17  *
  18  *       COPYRIGHT   I B M   CORPORATION 1995
  19  *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20  *-----------------------------------------------------------------------
  21  */
  22
  23 #include <config.h>
  24 #include <ppc4xx.h>
  25 #include "config.h"
  26
  27 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  28 #define FPGA_BRDC       0xF0300004
  29
  30 #include <ppc_asm.tmpl>
  31 #include <ppc_defs.h>
  32
  33 #include <asm/cache.h>
  34 #include <asm/mmu.h>
  35
  36 #include "exbitgen.h"
  37
  38 /* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */
  39 /* c-code declarations and consequently can't be included here). */
  40 /* (Possibly to be solved somehow else). */
  41 /*--------------------------------------------------------------------- */
  42 #define    I2C_REGISTERS_BASE_ADDRESS 0xEF600500
  43 #define    IIC_MDBUF    (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
  44 #define    IIC_SDBUF    (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
  45 #define    IIC_LMADR    (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
  46 #define    IIC_HMADR    (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
  47 #define    IIC_CNTL     (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
  48 #define    IIC_MDCNTL   (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
  49 #define    IIC_STS      (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
  50 #define    IIC_EXTSTS   (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
  51 #define    IIC_LSADR    (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
  52 #define    IIC_HSADR    (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
  53 #define    IIC_CLKDIV   (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
  54 #define    IIC_INTRMSK  (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
  55 #define    IIC_XFRCNT   (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
  56 #define    IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
  57 #define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
  58
  59 /* MDCNTL Register Bit definition */
  60 #define    IIC_MDCNTL_HSCL 0x01
  61 #define    IIC_MDCNTL_EUBS 0x02
  62 #define    IIC_MDCNTL_FMDB 0x40
  63 #define    IIC_MDCNTL_FSDB 0x80
  64
  65 /* CNTL Register Bit definition */
  66 #define    IIC_CNTL_PT     0x01
  67 #define    IIC_CNTL_READ   0x02
  68 #define    IIC_CNTL_CHT    0x04
  69
  70 /* STS Register Bit definition */
  71 #define    IIC_STS_PT      0X01
  72 #define    IIC_STS_ERR     0X04
  73 #define    IIC_STS_MDBS    0X20
  74
  75 /* EXTSTS Register Bit definition */
  76 #define    IIC_EXTSTS_XFRA 0X01
  77 #define    IIC_EXTSTS_ICT  0X02
  78 #define    IIC_EXTSTS_LA   0X04
  79
  80 /* LED codes used for inditing progress and errors during read of DIMM SPD.  */
  81 /*--------------------------------------------------------------------- */
  82 #define LED_SDRAM_CODE_1  0xef
  83 #define LED_SDRAM_CODE_2  0xee
  84 #define LED_SDRAM_CODE_3  0xed
  85 #define LED_SDRAM_CODE_4  0xec
  86 #define LED_SDRAM_CODE_5  0xeb
  87 #define LED_SDRAM_CODE_6  0xea
  88 #define LED_SDRAM_CODE_7  0xe9
  89 #define LED_SDRAM_CODE_8  0xe8
  90 #define LED_SDRAM_CODE_9  0xe7
  91 #define LED_SDRAM_CODE_10 0xe6
  92 #define LED_SDRAM_CODE_11 0xe5
  93 #define LED_SDRAM_CODE_12 0xe4
  94 #define LED_SDRAM_CODE_13 0xe3
  95 #define LED_SDRAM_CODE_14 0xe2
  96 #define LED_SDRAM_CODE_15 0xe1
  97 #define LED_SDRAM_CODE_16 0xe0
  98
  99
 100 #define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100
 101
 102 #define FLASH_8bit_AP   0x9B015480
 103 #define FLASH_8bit_CR   0xFFF18000 /* 1MB(min), 8bit, R/W */
 104
 105 #define FLASH_32bit_AP  0x9B015480
 106 #define FLASH_32bit_CR  0xFFE3C000 /* 2MB, 32bit, R/W */
 107
 108
 109 #define WDCR_EBC(reg,val) addi    r4,0,reg;\
 110         mtdcr   ebccfga,r4;\
 111         addis   r4,0,val@h;\
 112         ori     r4,r4,val@l;\
 113         mtdcr   ebccfgd,r4
 114
 115 /*---------------------------------------------------------------------
 116  * Function:     ext_bus_cntlr_init
 117  * Description:  Initializes the External Bus Controller for the external
 118  *              peripherals. IMPORTANT: For pass1 this code must run from
 119  *              cache since you can not reliably change a peripheral banks
 120  *              timing register (pbxap) while running code from that bank.
 121  *              For ex., since we are running from ROM on bank 0, we can NOT
 122  *              execute the code that modifies bank 0 timings from ROM, so
 123  *              we run it from cache.
 124  *      Bank 0 - Boot flash
 125  *      Bank 1-4 - application flash
 126  *      Bank 5 - CPLD
 127  *      Bank 6 - not used
 128  *      Bank 7 - Heathrow chip
 129  *---------------------------------------------------------------------
 130  */
 131         .globl  ext_bus_cntlr_init
 132 ext_bus_cntlr_init:
 133         mflr    r4                      /* save link register */
 134         bl      ..getAddr
 135 ..getAddr:
 136         mflr    r3                      /* get address of ..getAddr */
 137         mtlr    r4                      /* restore link register */
 138         addi    r4,0,14                 /* set ctr to 10; used to prefetch */
 139         mtctr   r4                      /* 10 cache lines to fit this function */
 140                                         /* in cache (gives us 8x10=80 instrctns) */
 141 ..ebcloop:
 142         icbt    r0,r3                   /* prefetch cache line for addr in r3 */
 143         addi    r3,r3,32                /* move to next cache line */
 144         bdnz    ..ebcloop               /* continue for 10 cache lines */
 145
 146         mflr    r31                     /* save link register */
 147
 148         /*-----------------------------------------------------------
 149          * Delay to ensure all accesses to ROM are complete before changing
 150          * bank 0 timings. 200usec should be enough.
 151          *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
 152          *-----------------------------------------------------------
 153          */
 154
 155         addis   r3,0,0x0
 156         ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
 157         mtctr   r3
 158 ..spinlp:
 159         bdnz    ..spinlp                /* spin loop */
 160
 161         /*---------------------------------------------------------------
 162          * Memory Bank 0 (Boot Flash) initialization
 163          *---------------------------------------------------------------
 164          */
 165         WDCR_EBC(pb0ap, FLASH_32bit_AP)
 166         WDCR_EBC(pb0cr, 0xffe38000)
 167 /*pnc   WDCR_EBC(pb0cr, FLASH_32bit_CR) */
 168
 169         /*---------------------------------------------------------------
 170          * Memory Bank 5 (CPLD) initialization
 171          *---------------------------------------------------------------
 172          */
 173         WDCR_EBC(pb5ap, 0x01010040)
 174 /*jsa recommendation:           WDCR_EBC(pb5ap, 0x00010040) */
 175         WDCR_EBC(pb5cr, 0x10038000)
 176
 177         /*--------------------------------------------------------------- */
 178         /* Memory Bank 6 (not used) initialization */
 179         /*--------------------------------------------------------------- */
 180         WDCR_EBC(pb6cr, 0x00000000)
 181
 182         /* Read HW ID to determine whether old H2 board or new generic CPU board */
 183         addis   r3, 0,  HW_ID_ADDR@h
 184         ori     r3, r3, HW_ID_ADDR@l
 185         lbz     r3,0x0000(r3)
 186         cmpi    0, r3, 1          /* if (HW_ID==1) */
 187         beq     setup_h2evalboard /* then jump */
 188         cmpi    0, r3, 2          /* if (HW_ID==2) */
 189         beq     setup_genieboard  /* then jump */
 190         cmpi    0, r3, 3          /* if (HW_ID==3) */
 191         beq     setup_genieboard  /* then jump */
 192
 193 setup_genieboard:
 194         /*--------------------------------------------------------------- */
 195         /* Memory Bank 1 (Application Flash) initialization for generic CPU board */
 196         /*--------------------------------------------------------------- */
 197 /*      WDCR_EBC(pb1ap, 0x7b015480)     /###* T.B.M. */
 198 /*      WDCR_EBC(pb1ap, 0x7F8FFE80)     /###* T.B.M. */
 199         WDCR_EBC(pb1ap, 0x9b015480)     /* hlb-20020207: burst 8 bit 6 cycles  */
 200
 201 /*      WDCR_EBC(pb1cr, 0x20098000)     /###* 16 MB */
 202         WDCR_EBC(pb1cr, 0x200B8000)     /* 32 MB */
 203
 204         /*--------------------------------------------------------------- */
 205         /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
 206         /*--------------------------------------------------------------- */
 207         WDCR_EBC(pb4ap, 0x01010000)     /*  */
 208         WDCR_EBC(pb4cr, 0x1021c000)     /*  */
 209
 210         /*--------------------------------------------------------------- */
 211         /* Memory Bank 7 (Heathrow chip on Reference board) initialization */
 212         /*--------------------------------------------------------------- */
 213         WDCR_EBC(pb7ap, 0x200ffe80)     /* No Ready, many wait states (let reflections die out) */
 214         WDCR_EBC(pb7cr, 0X4001A000)
 215
 216         bl      setup_continue
 217
 218
 219 setup_h2evalboard:
 220         /*--------------------------------------------------------------- */
 221         /* Memory Bank 1 (Application Flash) initialization */
 222         /*--------------------------------------------------------------- */
 223         WDCR_EBC(pb1ap, 0x7b015480)     /* T.B.M. */
 224 /*3010  WDCR_EBC(pb1ap, 0x7F8FFE80)     /###* T.B.M. */
 225         WDCR_EBC(pb1cr, 0x20058000)
 226
 227         /*--------------------------------------------------------------- */
 228         /* Memory Bank 2 (Application Flash) initialization */
 229         /*--------------------------------------------------------------- */
 230         WDCR_EBC(pb2ap, 0x7b015480)     /* T.B.M. */
 231 /*3010  WDCR_EBC(pb2ap, 0x7F8FFE80)     /###* T.B.M. */
 232         WDCR_EBC(pb2cr, 0x20458000)
 233
 234         /*--------------------------------------------------------------- */
 235         /* Memory Bank 3 (Application Flash) initialization */
 236         /*--------------------------------------------------------------- */
 237         WDCR_EBC(pb3ap, 0x7b015480)     /* T.B.M. */
 238 /*3010  WDCR_EBC(pb3ap, 0x7F8FFE80)     /###* T.B.M. */
 239         WDCR_EBC(pb3cr, 0x20858000)
 240
 241         /*--------------------------------------------------------------- */
 242         /* Memory Bank 4 (Application Flash) initialization */
 243         /*--------------------------------------------------------------- */
 244         WDCR_EBC(pb4ap, 0x7b015480)     /* T.B.M. */
 245 /*3010  WDCR_EBC(pb4ap, 0x7F8FFE80)     /###* T.B.M. */
 246         WDCR_EBC(pb4cr, 0x20C58000)
 247
 248         /*--------------------------------------------------------------- */
 249         /* Memory Bank 7 (Heathrow chip) initialization */
 250         /*--------------------------------------------------------------- */
 251         WDCR_EBC(pb7ap, 0x02000280)     /* No Ready, 4 wait states */
 252         WDCR_EBC(pb7cr, 0X4001A000)
 253
 254 setup_continue:
 255
 256
 257         mtlr    r31                     /* restore lr    */
 258         nop                             /* pass2 DCR errata #8 */
 259         blr
 260
 261 /*--------------------------------------------------------------------- */
 262 /* Function:     sdram_init */
 263 /* Description:  Configures SDRAM memory banks. */
 264 /*--------------------------------------------------------------------- */
 265         .globl  sdram_init
 266
 267 sdram_init:
 268 #if CFG_MONITOR_BASE < CFG_FLASH_BASE
 269         blr
 270 #else
 271         mflr    r31
 272
 273         /* output SDRAM code  on LEDs */
 274         addi    r4, 0, LED_SDRAM_CODE_1
 275         addis   r5, 0, 0x1000
 276         ori     r5, r5, 0x0001
 277         stb     r4,0(r5)
 278         eieio
 279
 280         /* Read contents of spd */
 281         /*--------------------- */
 282         bl      read_spd
 283
 284         /*----------------------------------------------------------- */
 285         /* */
 286         /* */
 287         /* Update SDRAM timing register */
 288         /* */
 289         /* */
 290         /*----------------------------------------------------------- */
 291
 292         /* Read  PLL feedback divider and calculate clock period of local bus in */
 293         /* granularity of 10 ps. Save clock period in r30 */
 294         /*-------------------------------------------------------------- */
 295         mfdcr   r4, pllmd
 296         addi    r9, 0, 25
 297         srw     r4, r4, r9
 298         andi.   r4, r4, 0x07
 299         addis   r5, 0,  TIMEBASE_10PS@h
 300         ori     r5, r5, TIMEBASE_10PS@l
 301         divwu   r30, r5, r4
 302
 303         /* Determine CASL */
 304         /*--------------- */
 305         bl      find_casl       /* Returns CASL in r3 */
 306
 307         /* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */
 308         /* (trp read from byte 27 in granularity of 1 ns) */
 309         /*------------------------------------------------ */
 310         mulli   r16, r16, 100
 311         add     r16, r16, r30
 312         addi    r6, 0, 1
 313         subf    r16, r6, r16
 314         divwu   r16, r16, r30
 315
 316         /* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */
 317         /* (trcd read from byte 29 in granularity of 1 ns) */
 318         /*--------------------------------------------------- */
 319         mulli   r17, r17, 100
 320         add     r17, r17, r30
 321         addi    r6, 0, 1
 322         subf    r17, r6, r17
 323         divwu   r17, r17, r30
 324
 325         /* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */
 326         /* (tras read from byte 30 in granularity of 1 ns) */
 327         /*--------------------------------------------------- */
 328         mulli   r18, r18, 100
 329         add     r18, r18, r30
 330         addi    r6, 0, 1
 331         subf    r18, r6, r18
 332         divwu   r18, r18, r30
 333
 334         /* Calc trc_clocks = trp_clocks + tras_clocks */
 335         /*------------------------------------------- */
 336         add     r18, r18, r16
 337
 338         /* CASL value */
 339         /*----------- */
 340         addi    r9, 0, 23
 341         slw     r4, r3, r9
 342
 343         /* PTA = trp_clocks - 1 */
 344         /*--------------------- */
 345         addi    r6, 0, 1
 346         subf    r5, r6, r16
 347         addi    r9, 0, 18
 348         slw     r5, r5, r9
 349         or      r4, r4, r5
 350
 351         /* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */
 352         /*------------------------------------------------ */
 353         addi    r5, r18, 0
 354         subf    r5, r16, r5
 355         subf    r5, r17, r5
 356         addi    r6, 0, 1
 357         subf    r5, r6, r5
 358         addi    r9, 0, 16
 359         slw     r5, r5, r9
 360         or      r4, r4, r5
 361
 362         /* LDF = 1 */
 363         /*-------- */
 364         ori     r4, r4, 0x4000
 365
 366         /* RFTA = trc_clocks - 4 */
 367         /*---------------------- */
 368         addi    r6, 0, 4
 369         subf    r5, r6, r18
 370         addi    r9, 0, 2
 371         slw     r5, r5, r9
 372         or      r4, r4, r5
 373
 374         /* RCD = trcd_clocks - 1 */
 375         /*---------------------- */
 376         addi    r6, 0, 1
 377         subf    r5, r6, r17
 378         or      r4, r4, r5
 379
 380         /*----------------------------------------------------------- */
 381         /* Set SDTR1  */
 382         /*----------------------------------------------------------- */
 383         addi    r5,0,mem_sdtr1
 384         mtdcr   memcfga,r5
 385         mtdcr   memcfgd,r4
 386
 387         /*----------------------------------------------------------- */
 388         /* */
 389         /* */
 390         /* Update memory bank 0-3 configuration registers */
 391         /* */
 392         /* */
 393         /*----------------------------------------------------------- */
 394
 395         /* Build contents of configuration register for bank 0 into r6 */
 396         /*------------------------------------------------------------ */
 397         bl      find_mode       /* returns addressing mode in r3 */
 398         addi    r29, r3, 0      /* save mode temporarily in r29 */
 399         bl      find_size_code  /* returns size code in r3 */
 400         addi    r9, 0, 17       /* bit offset of size code in configuration register */
 401         slw     r3, r3, r9      /* */
 402         addi    r9, 0, 13       /* bit offset of addressing mode in configuration register  */
 403         slw     r29, r29, r9    /*  */
 404         or      r3, r29, r3     /* merge size code and addressing mode */
 405         ori     r6, r3, CFG_SDRAM_BASE + 1 /* insert base address and enable bank */
 406
 407         /* Calculate banksize r15 = (density << 22) / 2 */
 408         /*--------------------------------------------- */
 409         addi    r9, 0, 21
 410         slw     r15, r15, r9
 411
 412         /* Set SDRAM bank 0 register and adjust r6 for next bank */
 413         /*------------------------------------------------------ */
 414         addi    r7,0,mem_mb0cf
 415         mtdcr   memcfga,r7
 416         mtdcr   memcfgd,r6
 417
 418         add     r6, r6, r15     /* add bank size to base address for next bank */
 419
 420         /* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */
 421         /*---------------------------------------------------------------------------- */
 422         cmpi    0, r12, 2
 423         bne     b1skip
 424
 425         addi    r7,0,mem_mb1cf
 426         mtdcr   memcfga,r7
 427         mtdcr   memcfgd,r6
 428
 429         add     r6, r6, r15     /* add bank size to base address for next bank */
 430
 431         /* Set SDRAM bank 2 register and adjust r6 for next bank */
 432         /*------------------------------------------------------ */
 433 b1skip: addi    r7,0,mem_mb2cf
 434         mtdcr   memcfga,r7
 435         mtdcr   memcfgd,r6
 436
 437         add     r6, r6, r15     /* add bank size to base address for next bank */
 438
 439         /* If two rows/banks then set SDRAM bank 3 register */
 440         /*------------------------------------------------ */
 441         cmpi    0, r12, 2
 442         bne     b3skip
 443
 444         addi    r7,0,mem_mb3cf
 445         mtdcr   memcfga,r7
 446         mtdcr   memcfgd,r6
 447 b3skip:
 448
 449         /*----------------------------------------------------------- */
 450         /* Set RTR */
 451         /*----------------------------------------------------------- */
 452         cmpi    0, r30, 1600
 453         bge     rtr_1
 454         addis   r7, 0, 0x05F0   /* RTR value for 100Mhz */
 455         bl      rtr_2
 456 rtr_1:  addis   r7, 0, 0x03F8
 457 rtr_2:  addi    r4,0,mem_rtr
 458         mtdcr   memcfga,r4
 459         mtdcr   memcfgd,r7
 460
 461         /*----------------------------------------------------------- */
 462         /* Delay to ensure 200usec have elapsed since reset. Assume worst */
 463         /* case that the core is running 200Mhz: */
 464         /*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
 465         /*----------------------------------------------------------- */
 466         addis   r3,0,0x0000
 467         ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
 468         mtctr   r3
 469 ..spinlp2:
 470         bdnz    ..spinlp2               /* spin loop */
 471
 472         /*----------------------------------------------------------- */
 473         /* Set memory controller options reg, MCOPT1. */
 474         /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst  */
 475         /* read/prefetch. */
 476         /*----------------------------------------------------------- */
 477         addi    r4,0,mem_mcopt1
 478         mtdcr   memcfga,r4
 479         addis   r4,0,0x80C0             /* set DC_EN=1 */
 480         ori     r4,r4,0x0000
 481         mtdcr   memcfgd,r4
 482
 483
 484         /*----------------------------------------------------------- */
 485         /* Delay to ensure 10msec have elapsed since reset. This is */
 486         /* required for the MPC952 to stabalize. Assume worst */
 487         /* case that the core is running 200Mhz: */
 488         /*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
 489         /* This delay should occur before accessing SDRAM. */
 490         /*----------------------------------------------------------- */
 491         addis   r3,0,0x001E
 492         ori     r3,r3,0x8480          /* ensure 10msec have passed since reset */
 493         mtctr   r3
 494 ..spinlp3:
 495         bdnz    ..spinlp3                /* spin loop */
 496
 497         /* output SDRAM code  on LEDs */
 498         addi    r4, 0, LED_SDRAM_CODE_16
 499         addis   r5, 0, 0x1000
 500         ori     r5, r5, 0x0001
 501         stb     r4,0(r5)
 502         eieio
 503
 504         mtlr    r31                     /* restore lr */
 505         blr
 506
 507 /*--------------------------------------------------------------------- */
 508 /* Function:    read_spd */
 509 /* Description: Reads contents of SPD and saves parameters to be used for */
 510 /*              configuration in dedicated registers (see code below). */
 511 /*---------------------------------------------------------------------  */
 512
 513 #define WRITE_I2C(reg,val) \
 514         addi    r3,0,val;\
 515         addis   r4, 0, 0xef60;\
 516         ori     r4, r4, 0x0500 + reg;\
 517         stb     r3, 0(r4);\
 518         eieio
 519
 520 #define READ_I2C(reg) \
 521         addis   r3, 0, 0xef60;\
 522         ori     r3, r3, 0x0500 + reg;\
 523         lbz     r3, 0x0000(r3);\
 524         eieio
 525
 526 read_spd:
 527
 528         mflr    r5
 529
 530         /* Initialize i2c */
 531         /*--------------- */
 532         WRITE_I2C(IICLMADR, 0x00)       /* clear lo master address */
 533         WRITE_I2C(IICHMADR, 0x00)       /* clear hi master address */
 534         WRITE_I2C(IICLSADR, 0x00)       /* clear lo slave address */
 535         WRITE_I2C(IICHSADR, 0x00)       /* clear hi slave address */
 536         WRITE_I2C(IICSTS, 0x08)         /* update status register */
 537         WRITE_I2C(IICEXTSTS, 0x8f)
 538         WRITE_I2C(IICCLKDIV, 0x05)
 539         WRITE_I2C(IICINTRMSK, 0x00)     /* no interrupts */
 540         WRITE_I2C(IICXFRCNT, 0x00)      /* clear transfer count */
 541         WRITE_I2C(IICXTCNTLSS, 0xf0)    /* clear extended control & stat */
 542         WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB) /* mode control */
 543         READ_I2C(IICMDCNTL)
 544         ori     r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL
 545         WRITE_I2C(IICMDCNTL, r3)        /* mode control */
 546         WRITE_I2C(IICCNTL, 0x00)        /* clear control reg */
 547
 548         /* Wait until initialization completed */
 549         /*------------------------------------ */
 550         bl      wait_i2c_transfer_done
 551
 552         WRITE_I2C(IICHMADR, 0x00)       /* 7-bit addressing */
 553         WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS)
 554
 555         /* Write 0 into buffer(start address) */
 556         /*----------------------------------- */
 557         WRITE_I2C(IICMDBUF, 0x00);
 558
 559         /* Wait a little */
 560         /*-------------- */
 561         addis   r3,0,0x0000
 562         ori     r3,r3,0xA000
 563         mtctr   r3
 564 in02:   bdnz    in02
 565
 566         /* Issue write command */
 567         /*-------------------- */
 568         WRITE_I2C(IICCNTL, IIC_CNTL_PT)
 569         bl      wait_i2c_transfer_done
 570
 571         /* Read 128 bytes */
 572         /*--------------- */
 573         addi    r7, 0, 0        /* byte counter in r7 */
 574         addi    r8, 0, 0        /* checksum in r8 */
 575 rdlp:
 576         /* issue read command */
 577         /*------------------- */
 578         cmpi    0, r7, 127
 579         blt     rd01
 580         WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT)
 581         bl      rd02
 582 rd01:   WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT)
 583 rd02:   bl      wait_i2c_transfer_done
 584
 585         /* Fetch byte from buffer */
 586         /*----------------------- */
 587         READ_I2C(IICMDBUF)
 588
 589         /* Retrieve parameters that are going to be used during configuration. */
 590         /* Save them in dedicated registers. */
 591         /*------------------------------------------------------------ */
 592         cmpi    0, r7, 3        /* Save byte 3 in r10 */
 593         bne     rd10
 594         addi    r10, r3, 0
 595 rd10:   cmpi    0, r7, 4        /* Save byte 4 in r11 */
 596         bne     rd11
 597         addi    r11, r3, 0
 598 rd11:   cmpi    0, r7, 5        /* Save byte 5 in r12 */
 599         bne     rd12
 600         addi    r12, r3, 0
 601 rd12:   cmpi    0, r7, 17       /* Save byte 17 in r13 */
 602         bne     rd13
 603         addi    r13, r3, 0
 604 rd13:   cmpi    0, r7, 18       /* Save byte 18 in r14 */
 605         bne     rd14
 606         addi    r14, r3, 0
 607 rd14:   cmpi    0, r7, 31       /* Save byte 31 in r15 */
 608         bne     rd15
 609         addi    r15, r3, 0
 610 rd15:   cmpi    0, r7, 27       /* Save byte 27 in r16 */
 611         bne     rd16
 612         addi    r16, r3, 0
 613 rd16:   cmpi    0, r7, 29       /* Save byte 29 in r17 */
 614         bne     rd17
 615         addi    r17, r3, 0
 616 rd17:   cmpi    0, r7, 30       /* Save byte 30 in r18 */
 617         bne     rd18
 618         addi    r18, r3, 0
 619 rd18:   cmpi    0, r7, 9        /* Save byte 9 in r19 */
 620         bne     rd19
 621         addi    r19, r3, 0
 622 rd19:   cmpi    0, r7, 23       /* Save byte 23 in r20 */
 623         bne     rd20
 624         addi    r20, r3, 0
 625 rd20:   cmpi    0, r7, 25       /* Save byte 25 in r21 */
 626         bne     rd21
 627         addi    r21, r3, 0
 628 rd21:
 629
 630         /* Calculate checksum of the first 63 bytes */
 631         /*----------------------------------------- */
 632         cmpi    0, r7, 63
 633         bgt     rd31
 634         beq     rd30
 635         add     r8, r8, r3
 636         bl      rd31
 637
 638         /* Verify checksum at byte 63 */
 639         /*--------------------------- */
 640 rd30:   andi.   r8, r8, 0xff            /* use only 8 bits */
 641         cmp     0, r8, r3
 642         beq     rd31
 643         addi    r4, 0, LED_SDRAM_CODE_8
 644         addis   r5, 0, 0x1000
 645         ori     r5, r5, 0x0001
 646         stb     r4,0(r5)
 647         eieio
 648 rderr:  bl      rderr
 649
 650 rd31:
 651
 652         /* Increment byte counter and check whether all bytes have been read. */
 653         /*------------------------------------------------------------------- */
 654         addi    r7, r7, 1
 655         cmpi    0, r7, 127
 656         bgt     rd05
 657         bl      rdlp
 658 rd05:
 659         mtlr    r5                     /* restore lr */
 660         blr
 661
 662 wait_i2c_transfer_done:
 663         mflr    r6
 664 wt01:   READ_I2C(IICSTS)
 665         andi.   r4, r3, IIC_STS_PT
 666         cmpi    0, r4, IIC_STS_PT
 667         beq     wt01
 668         mtlr    r6                     /* restore lr */
 669         blr
 670
 671 /*--------------------------------------------------------------------- */
 672 /* Function:    find_mode */
 673 /* Description: Determines addressing mode to be used dependent on   */
 674 /*              number of rows (r10 = byte 3 from SPD), number of columns (r11 = */
 675 /*              byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */
 676 /*              mode is returned in r3. */
 677 /* (It would be nicer having a table, pnc). */
 678 /*---------------------------------------------------------------------  */
 679 find_mode:
 680
 681         mflr    r5
 682
 683         cmpi    0, r10, 11
 684         bne     fm01
 685         cmpi    0, r11, 9
 686         bne     fm01
 687         cmpi    0, r13, 2
 688         bne     fm01
 689         addi    r3, 0, 1
 690         bl      fmfound
 691
 692 fm01:   cmpi    0, r10, 11
 693         bne     fm02
 694         cmpi    0, r11, 10
 695         bne     fm02
 696         cmpi    0, r13, 2
 697         bne     fm02
 698         addi    r3, 0, 1
 699         bl      fmfound
 700
 701 fm02:   cmpi    0, r10, 12
 702         bne     fm03
 703         cmpi    0, r11, 9
 704         bne     fm03
 705         cmpi    0, r13, 4
 706         bne     fm03
 707         addi    r3, 0, 2
 708         bl      fmfound
 709
 710 fm03:   cmpi    0, r10, 12
 711         bne     fm04
 712         cmpi    0, r11, 10
 713         bne     fm04
 714         cmpi    0, r13, 4
 715         bne     fm04
 716         addi    r3, 0, 2
 717         bl      fmfound
 718
 719 fm04:   cmpi    0, r10, 13
 720         bne     fm05
 721         cmpi    0, r11, 9
 722         bne     fm05
 723         cmpi    0, r13, 4
 724         bne     fm05
 725         addi    r3, 0, 3
 726         bl      fmfound
 727
 728 fm05:   cmpi    0, r10, 13
 729         bne     fm06
 730         cmpi    0, r11, 10
 731         bne     fm06
 732         cmpi    0, r13, 4
 733         bne     fm06
 734         addi    r3, 0, 3
 735         bl      fmfound
 736
 737 fm06:   cmpi    0, r10, 13
 738         bne     fm07
 739         cmpi    0, r11, 11
 740         bne     fm07
 741         cmpi    0, r13, 4
 742         bne     fm07
 743         addi    r3, 0, 3
 744         bl      fmfound
 745
 746 fm07:   cmpi    0, r10, 12
 747         bne     fm08
 748         cmpi    0, r11, 8
 749         bne     fm08
 750         cmpi    0, r13, 2
 751         bne     fm08
 752         addi    r3, 0, 4
 753         bl      fmfound
 754
 755 fm08:   cmpi    0, r10, 12
 756         bne     fm09
 757         cmpi    0, r11, 8
 758         bne     fm09
 759         cmpi    0, r13, 4
 760         bne     fm09
 761         addi    r3, 0, 4
 762         bl      fmfound
 763
 764 fm09:   cmpi    0, r10, 11
 765         bne     fm10
 766         cmpi    0, r11, 8
 767         bne     fm10
 768         cmpi    0, r13, 2
 769         bne     fm10
 770         addi    r3, 0, 5
 771         bl      fmfound
 772
 773 fm10:   cmpi    0, r10, 11
 774         bne     fm11
 775         cmpi    0, r11, 8
 776         bne     fm11
 777         cmpi    0, r13, 4
 778         bne     fm11
 779         addi    r3, 0, 5
 780         bl      fmfound
 781
 782 fm11:   cmpi    0, r10, 13
 783         bne     fm12
 784         cmpi    0, r11, 8
 785         bne     fm12
 786         cmpi    0, r13, 2
 787         bne     fm12
 788         addi    r3, 0, 6
 789         bl      fmfound
 790
 791 fm12:   cmpi    0, r10, 13
 792         bne     fm13
 793         cmpi    0, r11, 8
 794         bne     fm13
 795         cmpi    0, r13, 4
 796         bne     fm13
 797         addi    r3, 0, 6
 798         bl      fmfound
 799
 800 fm13:   cmpi    0, r10, 13
 801         bne     fm14
 802         cmpi    0, r11, 9
 803         bne     fm14
 804         cmpi    0, r13, 2
 805         bne     fm14
 806         addi    r3, 0, 7
 807         bl      fmfound
 808
 809 fm14:   cmpi    0, r10, 13
 810         bne     fm15
 811         cmpi    0, r11, 10
 812         bne     fm15
 813         cmpi    0, r13, 2
 814         bne     fm15
 815         addi    r3, 0, 7
 816         bl      fmfound
 817
 818 fm15:
 819         /* not found, error code to be issued on LEDs */
 820         addi    r7, 0, LED_SDRAM_CODE_2
 821         addis   r6, 0, 0x1000
 822         ori     r6, r6, 0x0001
 823         stb     r7,0(r6)
 824         eieio
 825 fmerr:  bl      fmerr
 826
 827 fmfound:addi    r6, 0, 1
 828         subf    r3, r6, r3
 829
 830         mtlr    r5                     /* restore lr */
 831         blr
 832
 833 /*--------------------------------------------------------------------- */
 834 /* Function:    find_size_code */
 835 /* Description: Determines size code to be used in configuring SDRAM controller */
 836 /*              dependent on density (r15 = byte 31 from SPD) */
 837 /*--------------------------------------------------------------------- */
 838 find_size_code:
 839
 840         mflr    r5
 841
 842         addi    r3, r15, 0      /* density */
 843         addi    r7, 0, 0
 844 fs01:   andi.   r6, r3, 0x01
 845         cmpi    0, r6, 1
 846         beq     fs04
 847
 848         addi    r7, r7, 1
 849         cmpi    0, r7, 7
 850         bge     fs02
 851         addi    r9, 0, 1
 852         srw     r3, r3, r9
 853         bl      fs01
 854
 855         /* not found, error code to be issued on LEDs */
 856 fs02:   addi    r4, 0, LED_SDRAM_CODE_3
 857         addis   r8, 0, 0x1000
 858         ori     r8, r8, 0x0001
 859         stb     r4,0(r8)
 860         eieio
 861 fs03:   bl      fs03
 862
 863 fs04:   addi    r3, r7, 0
 864         cmpi    0, r3, 0
 865         beq     fs05
 866         addi    r6, 0, 1
 867         subf    r3, r6, r3
 868 fs05:
 869         mtlr    r5                     /* restore lr */
 870         blr
 871
 872 /*--------------------------------------------------------------------- */
 873 /* Function:    find_casl */
 874 /* Description: Determines CAS latency */
 875 /*--------------------------------------------------------------------- */
 876 find_casl:
 877
 878         mflr    r5
 879
 880         andi.   r14, r14, 0x7f  /* r14 holds supported CAS latencies */
 881         addi    r3, 0, 0xff     /* preset determined CASL */
 882         addi    r4, 0, 6        /* Start at bit 6 of supported CAS latencies */
 883         addi    r2, 0, 0        /* Start finding highest CAS latency */
 884
 885 fc01:   srw     r6, r14, r4     /*  */
 886         andi.   r6, r6, 0x01    /*  */
 887         cmpi    0, r6, 1        /* Check bit for current latency */
 888         bne     fc06            /* If not supported, go to next */
 889
 890         cmpi    0, r2, 2        /* Check if third-highest latency */
 891         bge     fc04            /* If so, go calculate with another format */
 892
 893         cmpi    0, r2, 0        /* Check if highest latency */
 894         bgt     fc02            /* */
 895         addi    r7, r19, 0      /* SDRAM cycle time for highest CAS latenty */
 896
 897         bl      fc03
 898 fc02:
 899         addi    r7, r20, 0      /* SDRAM cycle time for next-highest CAS latenty */
 900 fc03:
 901         addi    r8, r7, 0
 902         addi    r9, 0, 4
 903         srw     r7, r7, r9
 904         andi.   r7, r7, 0x0f
 905         mulli   r7, r7, 100
 906         andi.   r8, r8, 0x0f
 907         mulli   r8, r8, 10
 908         add     r7, r7, r8
 909         cmp     0, r7, r30
 910         bgt     fc05
 911         addi    r3, r2, 0
 912         bl      fc05
 913 fc04:
 914         addi    r7, r21, 0      /* SDRAM cycle time for third-highest CAS latenty */
 915         addi    r8, r7, 0
 916         addi    r9, 0, 2
 917         srw     r7, r7, r9
 918         andi.   r7, r7, 0x3f
 919         mulli   r7, r7, 100
 920         andi.   r8, r8, 0x03
 921         mulli   r8, r8, 25
 922         add     r7, r7, r8
 923
 924         cmp     0, r7, r30
 925         bgt     fc05
 926         addi    r3, r2, 0
 927
 928 fc05:   addi    r2, r2, 1       /* next latency */
 929         cmpi    0, r2, 3
 930         bge     fc07
 931 fc06:   addi    r6, 0, 1
 932         subf    r4, r6, r4
 933         cmpi    0, r4, 0
 934         bne     fc01
 935
 936 fc07:
 937
 938         mtlr    r5              /* restore lr */
 939         blr
 940 #endif
 941
 942
 943 /*  Peripheral Bank 1 Access Parameters */
 944 /*     0        BME = 1 ; burstmode enabled */
 945 /*    " 1:8"    TWT=00110110    ;Transfer wait (details below) */
 946 /*     1:5      FWT=00110       ; first wait = 6 cycles */
 947 /*     6:8      BWT=110 ; burst wait = 6 cycles */
 948 /*     9:11     000     ; reserved */
 949 /*     12:13    CSN=00  ; chip select on timing = 0 */
 950 /*     14:15    OEN=01  ; output enable  */
 951 /*     16:17    WBN=01  ; write byte enable on timing 1 cycle */
 952 /*     18:19    WBF=01  ; write byte enable off timing 1 cycle */
 953 /*     20:22    TH=010  ; transfer hold = 2 cycles */
 954 /*     23       RE=0    ; ready enable = disabled */
 955 /*     24       SOR=1   ; sample on ready = same PerClk */
 956 /*     25       BEM=0   ; byte enable mode = only for write cycles */
 957 /*     26       PEN=0   ; parity enable = disable */
 958 /*     27:31    00000   ;reserved */
 959 /* */
 960 /* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */
 961 /* */
 962 /* */
 963 /*      Code for BDI probe: */
 964 /* */
 965 /* WDCR    18      0x00000011      ;Select PB1AP */
 966 /* WDCR    19      0x1b015480      ;PB1AP: Flash */
 967 /* */
 968 /* Peripheral Bank 0 Access Parameters */
 969 /* 0:11 BAS=0x200       ; base address select = 0x200 * 0x100000 (1MB) =  */
 970 /* 12:14        BS=100  ; bank size =  16MB (100) / 32MB (101) */
 971 /* 15:16        BU=11   ; bank usage = read/write */
 972 /* 17:18        BW=00   ; bus width = 8-bit */
 973 /* 19:31                ; reserved */
 974 /* */
 975 /* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */
 976 /* WDCR    18      0x00000001      ;Select PB1CR */
 977 /* WDCR    19      0x20098000      ;PB1CR: 1MB at 0x00100000, r/w, 8bit */
 978
 979 /* For CPLD */
 980 /* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */
 981 /*      WDCR_EBC(pb5ap, 0x01010040) */
 982 /*jsa recommendation:           WDCR_EBC(pb5ap, 0x00010040) */
 983 /*      WDCR_EBC(pb5cr, 0X10018000) */
 984 /* Access parms */
 985 /*   100   3      8          0    0    0 */
 986 /* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */
 987 /* Address :    0x10000000 */
 988 /* Size:        2 MB */
 989 /* Usage:       read/write */
 990 /* Width:       32 bit */
 991
 992 /* For Genie onboard fpga 32 bit interface */
 993 /* 0      1      0         1         0         0         0            0 */
 994 /* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */
 995 /* 0x01010000 */
 996 /* Access parms */
 997 /*   102   1      c          0    0    0 */
 998 /* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */
 999 /* Address :    0x10200000 */
1000 /* Size:        2 MB */
1001 /* Usage:       read/write */
1002 /* Width:       32 bit */
1003
1004 /* Walnut fpga pb7ap */
1005 /* 0      1      8         1         5         2         8            0 */
1006 /* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */
1007 /* Walnut fpga pb7cr */
1008 /* 0xF0318000 */
1009 /*  */