board/fads/fads.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
   6  * and Dan Malek
   7  *
   8  * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
   9  *
  10  * This header file contains values common to all FADS family boards.
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 /****************************************************************************
  16  * Flash Memory Map as used by U-Boot:
  17  *
  18  *                          Start Address    Length
  19  * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
  20  * |                       | 0xFE00_0100     Reset Vector
  21  * +                       + 0xFE0?_????
  22  * | U-Boot code           |
  23  * |                       |
  24  * +-----------------------+ 0xFE04_0000 (sector border)
  25  * |                       |
  26  * |                       |
  27  * | U-Boot environment    |
  28  * |                       |                                 ^
  29  * |                       |                                 | U-Boot
  30  * +=======================+ 0xFE08_0000 (sector border)    -----------------
  31  * | Available             |                                 | Applications
  32  * | ...                   |                                 v
  33  *
  34  *****************************************************************************/
  35
  36 #if 0
  37 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  38 #else
  39 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  40 #endif
  41
  42 #define CONFIG_ENV_OVERWRITE
  43
  44 #define CONFIG_NFSBOOTCOMMAND                                                   \
  45     "dhcp;"                                                                     \
  46     "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "                       \
  47     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  48     "bootm"
  49
  50 #define CONFIG_BOOTCOMMAND                                                      \
  51     "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
  52     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  53     "bootm fe080000"
  54
  55 #undef CONFIG_BOOTARGS
  56
  57 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  58
  59 #if !defined(CONFIG_MPC885ADS)
  60 #define CONFIG_BZIP2     /* include support for bzip2 compressed images */
  61 #endif
  62
  63 /*
  64  * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
  65  * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
  66  * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
  67  * got FEC so FEC is the default.
  68  */
  69 #ifndef CONFIG_ADS
  70 #undef  CONFIG_SCC1_ENET                /* Disable SCC1 ethernet */
  71 #define CONFIG_FEC_ENET                 /* Use FEC ethernet  */
  72 #else                                   /* Old ADS has not got FEC option */
  73 #define CONFIG_SCC1_ENET                /* Use SCC1 ethernet */
  74 #undef  CONFIG_FEC_ENET                 /* No FEC ethernet  */
  75 #endif /* !CONFIG_ADS */
  76
  77 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
  78 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
  79 #endif
  80
  81 #ifdef CONFIG_FEC_ENET
  82 #define CONFIG_SYS_DISCOVER_PHY
  83 #define CONFIG_MII_INIT         1
  84 #endif
  85
  86
  87 /*
  88  * BOOTP options
  89  */
  90 #define CONFIG_BOOTP_BOOTFILESIZE
  91 #define CONFIG_BOOTP_BOOTPATH
  92 #define CONFIG_BOOTP_GATEWAY
  93 #define CONFIG_BOOTP_HOSTNAME
  94
  95
  96 #if !defined(FADS_COMMANDS_ALREADY_DEFINED)
  97 /*
  98  * Command line configuration.
  99  */
 100 #include <config_cmd_default.h>
 101
 102 #define CONFIG_CMD_ASKENV
 103 #define CONFIG_CMD_DHCP
 104 #define CONFIG_CMD_ECHO
 105 #define CONFIG_CMD_IMMAP
 106 #define CONFIG_CMD_JFFS2
 107 #define CONFIG_CMD_MII
 108 #define CONFIG_CMD_PCMCIA
 109 #define CONFIG_CMD_PING
 110
 111 #endif
 112
 113
 114 /*
 115  * Miscellaneous configurable options
 116  */
 117 #define CONFIG_SYS_HUSH_PARSER
 118 #define CONFIG_SYS_LONGHELP                             /* #undef to save memory        */
 119 #if defined(CONFIG_CMD_KGDB)
 120 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
 121 #else
 122 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 123 #endif
 124 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size     */
 125 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 126 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 127
 128 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 129
 130 /*
 131  * Low Level Configuration Settings
 132  * (address mappings, register initial values, etc.)
 133  * You should know what you are doing if you make changes here.
 134  */
 135
 136 /*-----------------------------------------------------------------------
 137  * Internal Memory Mapped Register
 138  */
 139 #define CONFIG_SYS_IMMR         0xFF000000
 140
 141 /*-----------------------------------------------------------------------
 142  * Definitions for initial stack pointer and data area (in DPRAM)
 143  */
 144 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 145 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 146 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 147 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 148
 149 /*-----------------------------------------------------------------------
 150  * Start addresses for the final memory configuration
 151  * (Set up by the startup code)
 152  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 153  */
 154 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 155 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
 156 #define CONFIG_SYS_SDRAM_SIZE           0x00800000      /* 8 Mbyte */
 157 /*
 158  * 2048 SDRAM rows
 159  * 1000 factor s -> ms
 160  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 161  * 4    Number of refresh cycles per period
 162  * 64   Refresh cycle in ms per number of rows
 163  */
 164 #define CONFIG_SYS_PTA_PER_CLK          ((2048 * 64 * 1000) / (4 * 64))
 165 #elif defined(CONFIG_FADS)                              /* Old/new FADS */
 166 #define CONFIG_SYS_SDRAM_SIZE           0x00400000              /* 4 Mbyte */
 167 #else                                                   /* Old ADS */
 168 #define CONFIG_SYS_SDRAM_SIZE           0x00000000              /* No SDRAM */
 169 #endif
 170
 171 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 172 #if (CONFIG_SYS_SDRAM_SIZE)
 173 #define CONFIG_SYS_MEMTEST_END          CONFIG_SYS_SDRAM_SIZE   /* 1 ... SDRAM_SIZE     */
 174 #else
 175 #define CONFIG_SYS_MEMTEST_END          0x0400000       /* 1 ... 4 MB in DRAM   */
 176 #endif /* CONFIG_SYS_SDRAM_SIZE */
 177
 178 /*
 179  * For booting Linux, the board info and command line data
 180  * have to be in the first 8 MB of memory, since this is
 181  * the maximum mapped by the Linux kernel during initialization.
 182  */
 183 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 184
 185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 186 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 KB for monitor   */
 187
 188 #ifdef CONFIG_BZIP2
 189 #define CONFIG_SYS_MALLOC_LEN           (2500 << 10)    /* Reserve ~2.5 MB for malloc() */
 190 #else
 191 #define CONFIG_SYS_MALLOC_LEN           (384 << 10)     /* Reserve 384 kB for malloc()  */
 192 #endif /* CONFIG_BZIP2 */
 193
 194 /*-----------------------------------------------------------------------
 195  * Flash organization
 196  */
 197 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 198 #define CONFIG_SYS_FLASH_SIZE           ((uint)(8 * 1024 * 1024))       /* max 8Mbyte   */
 199
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      4       /* max number of memory banks           */
 201 #define CONFIG_SYS_MAX_FLASH_SECT       8       /* max number of sectors on one chip    */
 202
 203 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 204 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 205
 206 #define CONFIG_ENV_IS_IN_FLASH  1
 207 #define CONFIG_ENV_SECT_SIZE    0x40000 /* see README - env sector total size   */
 208 #define CONFIG_ENV_OFFSET               CONFIG_ENV_SECT_SIZE
 209 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment            */
 210 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 211
 212 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 213
 214 #if defined(CONFIG_CMD_JFFS2)
 215
 216 /*
 217  * JFFS2 partitions
 218  *
 219  */
 220 /* No command line, one static partition, whole device */
 221 #undef CONFIG_CMD_MTDPARTS
 222 #define CONFIG_JFFS2_DEV                "nor0"
 223 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 224 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 225
 226 /* mtdparts command line support */
 227 /* Note: fake mtd_id used, no linux mtd map file */
 228 /*
 229 #define CONFIG_CMD_MTDPARTS
 230 #define MTDIDS_DEFAULT          "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
 231 #define MTDPARTS_DEFAULT        "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
 232 */
 233
 234 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 235 #endif
 236
 237 /*-----------------------------------------------------------------------
 238  * Cache Configuration
 239  */
 240 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 241 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 242
 243 /*-----------------------------------------------------------------------
 244  * I2C configuration
 245  */
 246 #if defined(CONFIG_CMD_I2C)
 247 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 248 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address defaults */
 249 #define CONFIG_SYS_I2C_SLAVE            0x7F
 250 #endif
 251
 252 /*-----------------------------------------------------------------------
 253  * SYPCR - System Protection Control                            11-9
 254  * SYPCR can only be written once after reset!
 255  *-----------------------------------------------------------------------
 256  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 257  */
 258 #if defined(CONFIG_WATCHDOG)
 259 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 260                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 261 #else
 262 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 263 #endif
 264
 265 /*-----------------------------------------------------------------------
 266  * SIUMCR - SIU Module Configuration                            11-6
 267  *-----------------------------------------------------------------------
 268  * PCMCIA config., multi-function pin tri-state
 269  */
 270 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 271
 272 /*-----------------------------------------------------------------------
 273  * TBSCR - Time Base Status and Control                         11-26
 274  *-----------------------------------------------------------------------
 275  * Clear Reference Interrupt Status, Timebase freezing enabled
 276  */
 277 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 278
 279 /*-----------------------------------------------------------------------
 280  * PISCR - Periodic Interrupt Status and Control                11-31
 281  *-----------------------------------------------------------------------
 282  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 283  */
 284 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 285
 286 /*-----------------------------------------------------------------------
 287  * SCCR - System Clock and reset Control Register               15-27
 288  *-----------------------------------------------------------------------
 289  * Set clock output, timebase and RTC source and divider,
 290  * power management and some other internal clocks
 291  */
 292 #define SCCR_MASK       SCCR_EBDF11
 293 #define CONFIG_SYS_SCCR SCCR_TBS
 294
 295 /*-----------------------------------------------------------------------
 296  * DER - Debug Enable Register
 297  *-----------------------------------------------------------------------
 298  * Set to zero to prevent the processor from entering debug mode
 299  */
 300 #define CONFIG_SYS_DER           0
 301
 302 /* Because of the way the 860 starts up and assigns CS0 the entire
 303  * address space, we have to set the memory controller differently.
 304  * Normally, you write the option register first, and then enable the
 305  * chip select by writing the base register.  For CS0, you must write
 306  * the base register first, followed by the option register.
 307  */
 308
 309 /*
 310  * Init Memory Controller:
 311  *
 312  * BR0/OR0 (Flash)
 313  * BR1/OR1 (BCSR)
 314  */
 315 /* the other CS:s are determined by looking at parameters in BCSRx */
 316
 317 #define BCSR_ADDR               ((uint) 0xFF080000)
 318
 319 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000      /* OR addr mask */
 320
 321 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
 322 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 323
 324 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
 325 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V )
 326
 327 /* BCSRx - Board Control and Status Registers */
 328 #define CONFIG_SYS_OR1_PRELIM   0xFFFF8110              /* 64Kbyte address space */
 329 #define CONFIG_SYS_BR1_PRELIM   ((BCSR_ADDR) | BR_V)
 330
 331 /* values according to the manual */
 332
 333 #define BCSR0                   ((uint) (BCSR_ADDR + 0x00))
 334 #define BCSR1                   ((uint) (BCSR_ADDR + 0x04))
 335 #define BCSR2                   ((uint) (BCSR_ADDR + 0x08))
 336 #define BCSR3                   ((uint) (BCSR_ADDR + 0x0c))
 337 #define BCSR4                   ((uint) (BCSR_ADDR + 0x10))
 338
 339 /*
 340  * (F)ADS bitvalues by Helmut Buchsbaum
 341  *
 342  * See User's Manual for a proper
 343  * description of the following structures
 344  */
 345
 346 #define BCSR0_ERB       ((uint)0x80000000)
 347 #define BCSR0_IP        ((uint)0x40000000)
 348 #define BCSR0_BDIS      ((uint)0x10000000)
 349 #define BCSR0_BPS_MASK  ((uint)0x0C000000)
 350 #define BCSR0_ISB_MASK  ((uint)0x01800000)
 351 #define BCSR0_DBGC_MASK ((uint)0x00600000)
 352 #define BCSR0_DBPC_MASK ((uint)0x00180000)
 353 #define BCSR0_EBDF_MASK ((uint)0x00060000)
 354
 355 #define BCSR1_FLASH_EN           ((uint)0x80000000)
 356 #define BCSR1_DRAM_EN            ((uint)0x40000000)
 357 #define BCSR1_ETHEN              ((uint)0x20000000)
 358 #define BCSR1_IRDEN              ((uint)0x10000000)
 359 #define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
 360 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
 361 #define BCSR1_BCSR_EN            ((uint)0x02000000)
 362 #define BCSR1_RS232EN_1          ((uint)0x01000000)
 363 #define BCSR1_PCCEN              ((uint)0x00800000)
 364 #define BCSR1_PCCVCC0            ((uint)0x00400000)
 365 #define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
 366 #define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
 367 #define BCSR1_RS232EN_2          ((uint)0x00040000)
 368 #define BCSR1_SDRAM_EN           ((uint)0x00020000)
 369 #define BCSR1_PCCVCC1            ((uint)0x00010000)
 370
 371 #define BCSR1_PCCVCCON           BCSR1_PCCVCC0
 372
 373 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
 374 #define BCSR2_FLASH_PD_SHIFT     28
 375 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 376 #define BCSR2_DRAM_PD_SHIFT      23
 377 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
 378 #define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
 379
 380 #define BCSR3_DBID_MASK          ((ushort)0x3800)
 381 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
 382 #define BCSR3_BREVNR0            ((ushort)0x0080)
 383 #define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
 384 #define BCSR3_BREVN1             ((ushort)0x0008)
 385 #define BCSR3_BREVN2_MASK        ((ushort)0x0003)
 386
 387 #define BCSR4_ETHLOOP            ((uint)0x80000000)
 388 #define BCSR4_TFPLDL             ((uint)0x40000000)
 389 #define BCSR4_TPSQEL             ((uint)0x20000000)
 390 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
 391 #if defined(CONFIG_MPC823)
 392 #define BCSR4_USB_EN             ((uint)0x08000000)
 393 #define BCSR4_USB_SPEED          ((uint)0x04000000)
 394 #define BCSR4_VCCO               ((uint)0x02000000)
 395 #define BCSR4_VIDEO_ON           ((uint)0x00800000)
 396 #define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
 397 #define BCSR4_VIDEO_RST          ((uint)0x00200000)
 398 #define BCSR4_MODEM_EN           ((uint)0x00100000)
 399 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 400 #elif defined(CONFIG_MPC850)
 401 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 402 #elif defined(CONFIG_MPC860SAR)
 403 #define BCSR4_UTOPIA_EN          ((uint)0x08000000)
 404 #else /* MPC860T and other chips with FEC */
 405 #define BCSR4_FETH_EN            ((uint)0x08000000)
 406 #define BCSR4_FETHCFG0           ((uint)0x04000000)
 407 #define BCSR4_FETHFDE            ((uint)0x02000000)
 408 #define BCSR4_FETHCFG1           ((uint)0x00400000)
 409 #define BCSR4_FETHRST            ((uint)0x00200000)
 410 #endif
 411
 412 /* BSCR5 exists on MPC86xADS and MPC885ADS only */
 413
 414 #define CONFIG_SYS_PHYDEV_ADDR          (BCSR_ADDR + 0x20000)
 415
 416 #define BCSR5                   (CONFIG_SYS_PHYDEV_ADDR + 0x300)
 417
 418 #define BCSR5_MII2_EN           0x40
 419 #define BCSR5_MII2_RST          0x20
 420 #define BCSR5_T1_RST            0x10
 421 #define BCSR5_ATM155_RST        0x08
 422 #define BCSR5_ATM25_RST         0x04
 423 #define BCSR5_MII1_EN           0x02
 424 #define BCSR5_MII1_RST          0x01
 425
 426 /* We don't use the 8259.
 427 */
 428 #define NR_8259_INTS    0
 429
 430 /*-----------------------------------------------------------------------
 431  * PCMCIA stuff
 432  *-----------------------------------------------------------------------
 433  */
 434 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 435 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 436 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 437 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 438 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 439 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 440 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 441 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 442
 443 /*-----------------------------------------------------------------------
 444  * IDE/ATA stuff
 445  *-----------------------------------------------------------------------
 446  */
 447 #define CONFIG_MAC_PARTITION    1
 448 #define CONFIG_DOS_PARTITION    1
 449 #define CONFIG_ISO_PARTITION    1
 450
 451 #undef  CONFIG_ATAPI
 452 #if 0   /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
 453 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 454 #endif
 455 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 456 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 457 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 458
 459 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 2 IDE busses    */
 460 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 461
 462 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 463 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 464
 465 /* Offset for data I/O                  */
 466 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 467 /* Offset for normal register accesses  */
 468 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 469 /* Offset for alternate registers       */
 470 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000
 471
 472 #define CONFIG_DISK_SPINUP_TIME 1000000
 473 /* #undef CONFIG_DISK_SPINUP_TIME */    /* usin  Compact Flash */