2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 or later as published by the Free Software Foundation.
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
17 DECLARE_GLOBAL_DATA_PTR
;
19 dimm_params_t ddr_raw_timing
= {
21 .rank_density
= 2147483648u,
22 .capacity
= 4294967296u,
23 .primary_sdram_width
= 64,
29 .n_banks_per_sdram_device
= 8,
30 .edc_config
= 2, /* ECC */
31 .burst_lengths_bitmask
= 0x0c,
34 .caslat_X
= 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
45 .refresh_rate_ps
= 7800000,
49 int fsl_ddr_get_dimm_params(dimm_params_t
*pdimm
,
50 unsigned int controller_number
,
51 unsigned int dimm_number
)
53 const char dimm_model
[] = "RAW timing DDR";
55 if ((controller_number
== 0) && (dimm_number
== 0)) {
56 memcpy(pdimm
, &ddr_raw_timing
, sizeof(dimm_params_t
));
57 memset(pdimm
->mpart
, 0, sizeof(pdimm
->mpart
));
58 memcpy(pdimm
->mpart
, dimm_model
, sizeof(dimm_model
) - 1);
64 struct board_specific_parameters
{
66 u32 datarate_mhz_high
;
77 * This table contains all valid speeds we want to override with board
78 * specific parameters. datarate_mhz_high values need to be in ascending order
79 * for each n_ranks group.
81 static const struct board_specific_parameters udimm0
[] = {
84 * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
85 * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
87 {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
88 {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
89 {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
90 {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
91 {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
92 {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
96 static const struct board_specific_parameters
*udimms
[] = {
100 void fsl_ddr_board_options(memctl_options_t
*popts
,
101 dimm_params_t
*pdimm
,
102 unsigned int ctrl_num
)
104 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
108 printf("Not supported controller number %d\n", ctrl_num
);
117 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
118 * freqency and n_banks specified in board_specific_parameters table.
120 ddr_freq
= get_ddr_freq(0) / 1000000;
121 while (pbsp
->datarate_mhz_high
) {
122 if (pbsp
->n_ranks
== pdimm
->n_ranks
) {
123 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
124 popts
->cpo_override
= pbsp
->cpo
;
125 popts
->write_data_delay
=
126 pbsp
->write_data_delay
;
127 popts
->clk_adjust
= pbsp
->clk_adjust
;
128 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
129 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
130 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
131 popts
->twoT_en
= pbsp
->force_2T
;
140 printf("Error: board specific timing not found "
141 "for data rate %lu MT/s\n"
142 "Trying to use the highest speed (%u) parameters\n",
143 ddr_freq
, pbsp_highest
->datarate_mhz_high
);
144 popts
->cpo_override
= pbsp_highest
->cpo
;
145 popts
->write_data_delay
= pbsp_highest
->write_data_delay
;
146 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
147 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
148 popts
->twoT_en
= pbsp_highest
->force_2T
;
150 panic("DIMM is not supported by this board");
154 * Factors to consider for half-strength driver enable:
155 * - number of DIMMs installed
157 popts
->half_strength_driver_enable
= 0;
159 * Write leveling override
161 popts
->wrlvl_override
= 1;
162 popts
->wrlvl_sample
= 0xf;
165 * Rtt and Rtt_WR override
167 popts
->rtt_override
= 0;
169 /* Enable ZQ calibration */
172 /* DHC_EN =1, ODT = 75 Ohm */
173 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm
);
174 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_75ohm
);
177 phys_size_t
initdram(int board_type
)
179 phys_size_t dram_size
;
181 puts("Initializing....using SPD\n");
183 dram_size
= fsl_ddr_sdram();
185 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
186 dram_size
*= 0x100000;