1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
9 struct fsl_e_tlb_entry tlb_table
[] = {
10 /* TLB 0 - for temp stack in cache */
11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
,
12 CONFIG_SYS_INIT_RAM_ADDR_PHYS
,
13 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
14 0, 0, BOOKE_PAGESZ_4K
, 0),
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 4 * 1024,
16 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 4 * 1024,
17 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
18 0, 0, BOOKE_PAGESZ_4K
, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 8 * 1024,
20 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 8 * 1024,
21 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
22 0, 0, BOOKE_PAGESZ_4K
, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 12 * 1024,
24 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 12 * 1024,
25 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
26 0, 0, BOOKE_PAGESZ_4K
, 0),
29 /* *I*** - Covers boot page */
30 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
32 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
33 * SRAM is at 0xfff00000, it covered the 0xfffff000.
35 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR
, CONFIG_SYS_INIT_L3_ADDR
,
36 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
37 0, 0, BOOKE_PAGESZ_1M
, 1),
38 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
40 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
41 * space is at 0xfff00000, it covered the 0xfffff000.
43 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
,
44 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS
,
45 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_W
|MAS2_G
,
46 0, 0, BOOKE_PAGESZ_1M
, 1),
48 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
49 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
50 0, 0, BOOKE_PAGESZ_4K
, 1),
54 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR
, CONFIG_SYS_CCSRBAR_PHYS
,
55 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
56 0, 1, BOOKE_PAGESZ_16M
, 1),
58 /* *I*G* - Flash, localbus */
59 /* This will be changed to *I*G* after relocation to RAM. */
60 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FLASH_BASE_PHYS
,
61 MAS3_SX
|MAS3_SR
, MAS2_W
|MAS2_G
,
62 0, 2, BOOKE_PAGESZ_256M
, 1),
64 #ifndef CONFIG_SPL_BUILD
66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT
, CONFIG_SYS_PCIE1_MEM_PHYS
,
67 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
68 0, 3, BOOKE_PAGESZ_256M
, 1),
70 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT
+ 0x10000000,
71 CONFIG_SYS_PCIE1_MEM_PHYS
+ 0x10000000,
72 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
73 0, 4, BOOKE_PAGESZ_256M
, 1),
76 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT
, CONFIG_SYS_PCIE1_IO_PHYS
,
77 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
78 0, 5, BOOKE_PAGESZ_64K
, 1),
81 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
82 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
, CONFIG_SYS_BMAN_MEM_PHYS
,
83 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
84 0, 6, BOOKE_PAGESZ_16M
, 1),
85 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
+ 0x01000000,
86 CONFIG_SYS_BMAN_MEM_PHYS
+ 0x01000000,
87 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
88 0, 7, BOOKE_PAGESZ_16M
, 1),
90 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
91 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
, CONFIG_SYS_QMAN_MEM_PHYS
,
92 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
93 0, 8, BOOKE_PAGESZ_16M
, 1),
94 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
+ 0x01000000,
95 CONFIG_SYS_QMAN_MEM_PHYS
+ 0x01000000,
96 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
97 0, 9, BOOKE_PAGESZ_16M
, 1),
100 #ifdef CONFIG_SYS_DCSRBAR_PHYS
101 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR
, CONFIG_SYS_DCSRBAR_PHYS
,
102 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
103 0, 10, BOOKE_PAGESZ_32M
, 1),
105 #ifdef CONFIG_SYS_NAND_BASE
109 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE
, CONFIG_SYS_NAND_BASE_PHYS
,
110 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
111 0, 11, BOOKE_PAGESZ_64K
, 1),
113 SET_TLB_ENTRY(1, QIXIS_BASE
, QIXIS_BASE_PHYS
,
114 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
115 0, 12, BOOKE_PAGESZ_4K
, 1),
119 * entry 14 and 15 has been used hard coded, they will be disabled
120 * in cpu_init_f, so we use entry 16 for SRIO2.
122 #ifndef CONFIG_SPL_BUILD
123 #ifdef CONFIG_SYS_SRIO1_MEM_PHYS
125 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT
, CONFIG_SYS_SRIO1_MEM_PHYS
,
126 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
127 0, 13, BOOKE_PAGESZ_256M
, 1),
129 #ifdef CONFIG_SYS_SRIO2_MEM_PHYS
131 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT
, CONFIG_SYS_SRIO2_MEM_PHYS
,
132 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
133 0, 16, BOOKE_PAGESZ_256M
, 1),
135 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
137 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
138 * fetching ucode and ENV from master
140 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR
,
141 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS
,
142 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_G
,
143 0, 17, BOOKE_PAGESZ_1M
, 1),
147 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
148 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE
, CONFIG_SYS_DDR_SDRAM_BASE
,
149 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_M
,
150 0, 17, BOOKE_PAGESZ_2G
, 1)
154 int num_tlb_entries
= ARRAY_SIZE(tlb_table
);