board/freescale/b4860qds/tlb.c

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/mmu.h>
  25
  26 struct fsl_e_tlb_entry tlb_table[] = {
  27         /* TLB 0 - for temp stack in cache */
  28         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  29                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  30                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  31                       0, 0, BOOKE_PAGESZ_4K, 0),
  32         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  33                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  34                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  35                       0, 0, BOOKE_PAGESZ_4K, 0),
  36         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  37                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  38                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  39                       0, 0, BOOKE_PAGESZ_4K, 0),
  40         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  41                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  42                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  43                       0, 0, BOOKE_PAGESZ_4K, 0),
  44
  45         /* TLB 1 */
  46         /* *I*** - Covers boot page */
  47 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  48         /*
  49          * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  50          * SRAM is at 0xfff00000, it covered the 0xfffff000.
  51          */
  52         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  53                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                         0, 0, BOOKE_PAGESZ_1M, 1),
  55 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  56         /*
  57          * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
  58          * space is at 0xfff00000, it covered the 0xfffff000.
  59          */
  60         SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
  61                       CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  62                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
  63                       0, 0, BOOKE_PAGESZ_1M, 1),
  64 #else
  65         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  66                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  67                       0, 0, BOOKE_PAGESZ_4K, 1),
  68 #endif
  69
  70         /* *I*G* - CCSRBAR */
  71         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  72                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73                       0, 1, BOOKE_PAGESZ_16M, 1),
  74
  75         /* *I*G* - Flash, localbus */
  76         /* This will be changed to *I*G* after relocation to RAM. */
  77         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  78                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  79                       0, 2, BOOKE_PAGESZ_256M, 1),
  80
  81         /* *I*G* - PCI */
  82         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  83                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  84                       0, 3, BOOKE_PAGESZ_256M, 1),
  85
  86         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
  87                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
  88                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  89                       0, 4, BOOKE_PAGESZ_256M, 1),
  90
  91         /* *I*G* - PCI I/O */
  92         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  93                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  94                       0, 5, BOOKE_PAGESZ_64K, 1),
  95
  96         /* Bman/Qman */
  97 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  98         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  99                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
 100                       0, 6, BOOKE_PAGESZ_16M, 1),
 101         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
 102                       CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
 103                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 104                       0, 7, BOOKE_PAGESZ_16M, 1),
 105 #endif
 106 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
 107         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
 108                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
 109                       0, 8, BOOKE_PAGESZ_16M, 1),
 110         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
 111                       CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
 112                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 113                       0, 9, BOOKE_PAGESZ_16M, 1),
 114 #endif
 115 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 116         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 117                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 118                       0, 10, BOOKE_PAGESZ_32M, 1),
 119 #endif
 120 #ifdef CONFIG_SYS_NAND_BASE
 121         /*
 122          * *I*G - NAND
 123          */
 124         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 125                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 126                         0, 11, BOOKE_PAGESZ_64K, 1),
 127 #endif
 128         SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
 129                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 130                       0, 12, BOOKE_PAGESZ_4K, 1),
 131
 132         /*
 133          * *I*G - SRIO
 134          * entry 14 and 15 has been used hard coded, they will be disabled
 135          * in cpu_init_f, so we use entry 16 for SRIO2.
 136          */
 137 #ifdef CONFIG_SYS_SRIO1_MEM_PHYS
 138         /* *I*G* - SRIO1 */
 139         SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
 140                 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 141                       0, 13, BOOKE_PAGESZ_256M, 1),
 142 #endif
 143 #ifdef CONFIG_SYS_SRIO2_MEM_PHYS
 144         /* *I*G* - SRIO2 */
 145         SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
 146                 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 147                       0, 16, BOOKE_PAGESZ_256M, 1),
 148 #endif
 149 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 150         /*
 151          * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
 152          * fetching ucode and ENV from master
 153          */
 154         SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
 155                       CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 156                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 157                       0, 17, BOOKE_PAGESZ_1M, 1),
 158 #endif
 159 };
 160
 161 int num_tlb_entries = ARRAY_SIZE(tlb_table);