2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/fsl_law.h>
9 #include <fsl_ddr_sdram.h>
10 #include <fsl_ddr_dimm_params.h>
14 #define C29XPCIE_HARDWARE_REVA 0x40
16 * Micron MT41J128M16HA-15E
18 dimm_params_t ddr_raw_timing
= {
20 .rank_density
= 536870912u,
21 .capacity
= 536870912u,
22 .primary_sdram_width
= 32,
28 .n_banks_per_sdram_device
= 8,
30 .burst_lengths_bitmask
= 0x0c,
33 .caslat_x
= 0x7e << 4, /* 5,6,7,8,9,10 */
44 .refresh_rate_ps
= 7800000,
48 int fsl_ddr_get_dimm_params(dimm_params_t
*pdimm
,
49 unsigned int controller_number
,
50 unsigned int dimm_number
)
52 const char dimm_model
[] = "Fixed DDR on board";
54 if ((controller_number
== 0) && (dimm_number
== 0)) {
55 memcpy(pdimm
, &ddr_raw_timing
, sizeof(dimm_params_t
));
56 memset(pdimm
->mpart
, 0, sizeof(pdimm
->mpart
));
57 memcpy(pdimm
->mpart
, dimm_model
, sizeof(dimm_model
) - 1);
63 void fsl_ddr_board_options(memctl_options_t
*popts
,
65 unsigned int ctrl_num
)
67 struct cpld_data
*cpld_data
= (void *)(CONFIG_SYS_CPLD_BASE
);
70 popts
->clk_adjust
= 4;
71 popts
->cpo_override
= 0x1f;
72 popts
->write_data_delay
= 4;
73 popts
->half_strength_driver_enable
= 1;
74 popts
->bstopre
= 0x3cf;
75 popts
->quad_rank_present
= 1;
76 popts
->rtt_override
= 1;
77 popts
->rtt_override_value
= 1;
78 popts
->dynamic_power
= 1;
79 /* Write leveling override */
81 popts
->wrlvl_override
= 1;
82 popts
->wrlvl_sample
= 0xf;
83 popts
->wrlvl_start
= 0x4;
84 popts
->trwt_override
= 1;
87 if (in_8(&cpld_data
->hwver
) == C29XPCIE_HARDWARE_REVA
)
90 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
91 popts
->cs_local_opts
[i
].odt_rd_cfg
= FSL_DDR_ODT_NEVER
;
92 popts
->cs_local_opts
[i
].odt_wr_cfg
= FSL_DDR_ODT_CS
;