2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl_validate.h>
12 #include <asm/arch/immap_ls102xa.h>
15 #if defined(CONFIG_MPC85xx)
16 #define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
18 #define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
21 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
22 #define gur_in32(a) in_le32(a)
24 #define gur_in32(a) in_be32(a)
27 /* Check the Boot Mode. If Secure, return 1 else return 0 */
28 int fsl_check_boot_mode_secure(void)
31 struct ccsr_sfp_regs
*sfp_regs
= (void *)(CONFIG_SYS_SFP_ADDR
);
32 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_DCFG_ADDR
);
34 val
= sfp_in32(&sfp_regs
->ospr
) & ITS_MASK
;
38 #if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx)
39 /* For PBL based platforms check the SB_EN bit in RCWSR */
40 val
= gur_in32(&gur
->rcwsr
[RCW_SB_EN_REG_INDEX
- 1]) & RCW_SB_EN_MASK
;
41 if (val
== RCW_SB_EN_MASK
)
45 #if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET)
46 /* For Non-PBL Platforms, check the Device Status register 2*/
47 val
= gur_in32(&gur
->pordevsr2
) & MPC85xx_PORDEVSR2_SBC_MASK
;
48 if (val
!= MPC85xx_PORDEVSR2_SBC_MASK
)