2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
33 static ulong
strfractoint(uchar
*strptr
);
39 void pixis_reset(void)
41 out8(PIXIS_BASE
+ PIXIS_RST
, 0);
46 * Per table 27, page 58 of MPC8641HPCN spec.
48 int set_px_sysclk(ulong sysclk
)
50 u8 sysclk_s
, sysclk_r
, sysclk_v
, vclkh
, vclkl
, sysclk_aux
;
102 printf("Unsupported SYSCLK frequency.\n");
106 vclkh
= (sysclk_s
<< 5) | sysclk_r
;
109 out8(PIXIS_BASE
+ PIXIS_VCLKH
, vclkh
);
110 out8(PIXIS_BASE
+ PIXIS_VCLKL
, vclkl
);
112 out8(PIXIS_BASE
+ PIXIS_AUX
, sysclk_aux
);
118 int set_px_mpxpll(ulong mpxpll
)
135 printf("Unsupported MPXPLL ratio.\n");
139 tmp
= in8(PIXIS_BASE
+ PIXIS_VSPEED1
);
140 tmp
= (tmp
& 0xF0) | (val
& 0x0F);
141 out8(PIXIS_BASE
+ PIXIS_VSPEED1
, tmp
);
147 int set_px_corepll(ulong corepll
)
152 switch ((int)corepll
) {
172 printf("Unsupported COREPLL ratio.\n");
176 tmp
= in8(PIXIS_BASE
+ PIXIS_VSPEED0
);
177 tmp
= (tmp
& 0xE0) | (val
& 0x1F);
178 out8(PIXIS_BASE
+ PIXIS_VSPEED0
, tmp
);
184 void read_from_px_regs(int set
)
187 u8 tmp
= in8(PIXIS_BASE
+ PIXIS_VCFGEN0
);
193 out8(PIXIS_BASE
+ PIXIS_VCFGEN0
, tmp
);
197 void read_from_px_regs_altbank(int set
)
200 u8 tmp
= in8(PIXIS_BASE
+ PIXIS_VCFGEN1
);
206 out8(PIXIS_BASE
+ PIXIS_VCFGEN1
, tmp
);
210 void set_altbank(void)
214 tmp
= in8(PIXIS_BASE
+ PIXIS_VBOOT
);
217 out8(PIXIS_BASE
+ PIXIS_VBOOT
, tmp
);
225 tmp
= in8(PIXIS_BASE
+ PIXIS_VCTL
);
227 out8(PIXIS_BASE
+ PIXIS_VCTL
, tmp
);
229 tmp
= in8(PIXIS_BASE
+ PIXIS_VCTL
);
231 out8(PIXIS_BASE
+ PIXIS_VCTL
, tmp
);
235 void set_px_go_with_watchdog(void)
239 tmp
= in8(PIXIS_BASE
+ PIXIS_VCTL
);
241 out8(PIXIS_BASE
+ PIXIS_VCTL
, tmp
);
243 tmp
= in8(PIXIS_BASE
+ PIXIS_VCTL
);
245 out8(PIXIS_BASE
+ PIXIS_VCTL
, tmp
);
249 int pixis_disable_watchdog_cmd(cmd_tbl_t
*cmdtp
,
250 int flag
, int argc
, char *argv
[])
254 tmp
= in8(PIXIS_BASE
+ PIXIS_VCTL
);
256 out8(PIXIS_BASE
+ PIXIS_VCTL
, tmp
);
258 /* setting VCTL[WDEN] to 0 to disable watch dog */
259 tmp
= in8(PIXIS_BASE
+ PIXIS_VCTL
);
261 out8(PIXIS_BASE
+ PIXIS_VCTL
, tmp
);
267 diswd
, 1, 0, pixis_disable_watchdog_cmd
,
268 "diswd - Disable watchdog timer \n",
272 * This function takes the non-integral cpu:mpx pll ratio
273 * and converts it to an integer that can be used to assign
274 * FPGA register values.
275 * input: strptr i.e. argv[2]
278 static ulong
strfractoint(uchar
*strptr
)
282 int intarr_len
= 0, decarr_len
= 0, no_dec
= 0;
283 ulong intval
= 0, decval
= 0;
284 uchar intarr
[3], decarr
[3];
286 /* Assign the integer part to intarr[]
287 * If there is no decimal point i.e.
288 * if the ratio is an integral value
289 * simply create the intarr.
292 while (strptr
[i
] != 46) {
293 if (strptr
[i
] == 0) {
297 intarr
[i
] = strptr
[i
];
301 /* Assign length of integer part to intarr_len. */
306 /* Currently needed only for single digit corepll ratios */
311 i
++; /* Skipping the decimal point */
312 while ((strptr
[i
] > 47) && (strptr
[i
] < 58)) {
313 decarr
[j
] = strptr
[i
];
322 for (i
= 0; i
< decarr_len
; i
++)
324 decval
= simple_strtoul(decarr
, NULL
, 10);
327 intval
= simple_strtoul(intarr
, NULL
, 10);
328 intval
= intval
* mulconst
;
330 retval
= intval
+ decval
;
337 pixis_reset_cmd(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
343 * No args is a simple reset request.
350 if (strcmp(argv
[1], "cf") == 0) {
353 * Reset with frequency changed:
354 * cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
361 read_from_px_regs(0);
363 val
= set_px_sysclk(simple_strtoul(argv
[2], NULL
, 10));
365 corepll
= strfractoint(argv
[3]);
366 val
= val
+ set_px_corepll(corepll
);
367 val
= val
+ set_px_mpxpll(simple_strtoul(argv
[4], NULL
, 10));
369 puts("Setting registers VCFGEN0 and VCTL\n");
370 read_from_px_regs(1);
371 puts("Resetting board with values from ");
372 puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
379 while (1) ; /* Not reached */
381 } else if (strcmp(argv
[1], "altbank") == 0) {
384 * Reset using alternate flash bank:
388 * Reset from alternate bank without changing
389 * frequency and without watchdog timer enabled.
392 read_from_px_regs(0);
393 read_from_px_regs_altbank(0);
398 puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
400 read_from_px_regs_altbank(1);
401 puts("Resetting board to boot from the other bank.\n");
404 } else if (strcmp(argv
[2], "cf") == 0) {
406 * Reset with frequency changed
407 * altbank cf <SYSCLK freq> <COREPLL ratio>
410 read_from_px_regs(0);
411 read_from_px_regs_altbank(0);
412 val
= set_px_sysclk(simple_strtoul(argv
[3], NULL
, 10));
413 corepll
= strfractoint(argv
[4]);
414 val
= val
+ set_px_corepll(corepll
);
415 val
= val
+ set_px_mpxpll(simple_strtoul(argv
[5],
418 puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
420 read_from_px_regs(1);
421 read_from_px_regs_altbank(1);
422 puts("Enabling watchdog timer on the FPGA\n");
423 puts("Resetting board with values from ");
424 puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
425 puts("to boot from the other bank.\n");
426 set_px_go_with_watchdog();
432 while (1) ; /* Not reached */
434 } else if (strcmp(argv
[2], "wd") == 0) {
436 * Reset from alternate bank without changing
437 * frequencies but with watchdog timer enabled:
440 read_from_px_regs(0);
441 read_from_px_regs_altbank(0);
442 puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
444 read_from_px_regs_altbank(1);
445 puts("Enabling watchdog timer on the FPGA\n");
446 puts("Resetting board to boot from the other bank.\n");
447 set_px_go_with_watchdog();
448 while (1) ; /* Not reached */
465 pixis_reset
, CFG_MAXARGS
, 1, pixis_reset_cmd
,
466 "pixis_reset - Reset the board using the FPGA sequencer\n",
468 " pixis_reset [altbank]\n"
469 " pixis_reset altbank wd\n"
470 " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
471 " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"