board/freescale/common/qixis.h

   1 /*
   2  * Copyright 2011 Freescale Semiconductor
   3  * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * This file provides support for the QIXIS of some Freescale reference boards.
   8  */
   9
  10 #ifndef __QIXIS_H_
  11 #define __QIXIS_H_
  12
  13 struct qixis {
  14         u8 id;      /* ID value uniquely identifying each QDS board type */
  15         u8 arch;    /* Board version information */
  16         u8 scver;   /* QIXIS Version Register */
  17         u8 model;   /* Information of software programming model version */
  18         u8 tagdata;
  19         u8 ctl_sys;
  20         u8 aux;         /* Auxiliary Register,0x06 */
  21         u8 clk_spd;
  22         u8 stat_dut;
  23         u8 stat_sys;
  24         u8 stat_alrm;
  25         u8 present;
  26         u8 present2;    /* Presence Status Register 2,0x0c */
  27         u8 rcw_ctl;
  28         u8 ctl_led;
  29         u8 i2cblk;
  30         u8 rcfg_ctl;    /* Reconfig Control Register,0x10 */
  31         u8 rcfg_st;
  32         u8 dcm_ad;
  33         u8 dcm_da;
  34         u8 dcmd;
  35         u8 dmsg;
  36         u8 gdc;
  37         u8 gdd;         /* DCM Debug Data Register,0x17 */
  38         u8 dmack;
  39         u8 res1[6];
  40         u8 watch;       /* Watchdog Register,0x1F */
  41         u8 pwr_ctl[2];  /* Power Control Register,0x20 */
  42         u8 res2[2];
  43         u8 pwr_stat[4]; /* Power Status Register,0x24 */
  44         u8 res3[8];
  45         u8 clk_spd2[2];  /* SYSCLK clock Speed Register,0x30 */
  46         u8 res4[2];
  47         u8 sclk[3];  /* Clock Configuration Registers,0x34 */
  48         u8 res5;
  49         u8 dclk[3];
  50         u8 res6;
  51         u8 clk_dspd[3];
  52         u8 res7;
  53         u8 rst_ctl;     /* Reset Control Register,0x40 */
  54         u8 rst_stat;    /* Reset Status Register */
  55         u8 rst_rsn;     /* Reset Reason Register */
  56         u8 rst_frc[2];  /* Reset Force Registers,0x43 */
  57         u8 res8[11];
  58         u8 brdcfg[16];  /* Board Configuration Register,0x50 */
  59         u8 dutcfg[16];
  60         u8 rcw_ad[2];   /* RCW SRAM Address Registers,0x70 */
  61         u8 rcw_data;
  62         u8 res9[5];
  63         u8 post_ctl;
  64         u8 post_stat;
  65         u8 post_dat[2];
  66         u8 pi_d[4];
  67         u8 gpio_io[4];
  68         u8 gpio_dir[4];
  69         u8 res10[20];
  70         u8 rjtag_ctl;
  71         u8 rjtag_dat;
  72         u8 res11[2];
  73         u8 trig_src[4];
  74         u8 trig_dst[4];
  75         u8 trig_stat;
  76         u8 res12[3];
  77         u8 trig_ctr[4];
  78         u8 res13[16];
  79         u8 clk_freq[6]; /* Clock Measurement Registers */
  80         u8 res_c6[8];
  81         u8 clk_base[2]; /* Clock Frequency Base Reg */
  82         u8 res_d0[16];
  83         u8 aux2[4];     /* Auxiliary Registers,0xE0 */
  84         u8 res14[10];
  85         u8 aux_ad;
  86         u8 aux_da;
  87         u8 res15[16];
  88 };
  89
  90 u8 qixis_read(unsigned int reg);
  91 void qixis_write(unsigned int reg, u8 value);
  92 u16 qixis_read_minor(void);
  93 char *qixis_read_time(char *result);
  94 char *qixis_read_tag(char *buf);
  95 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
  96 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
  97 u8 qixis_read_i2c(unsigned int reg);
  98 void qixis_write_i2c(unsigned int reg, u8 value);
  99 #endif
 100
 101 #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
 102 #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
 103 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 104 #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
 105 #define QIXIS_WRITE_I2C(reg, value) \
 106                         qixis_write_i2c(offsetof(struct qixis, reg), value)
 107 #endif
 108
 109 #endif