board/freescale/corenet_ds/corenet_ds.c

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <netdev.h>
  10 #include <linux/compiler.h>
  11 #include <asm/mmu.h>
  12 #include <asm/processor.h>
  13 #include <asm/cache.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <fm_eth.h>
  20
  21 #include "../common/ngpixis.h"
  22 #include "corenet_ds.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 int checkboard (void)
  27 {
  28         u8 sw;
  29         struct cpu_type *cpu = gd->arch.cpu;
  30 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \
  31         defined(CONFIG_P5040DS)
  32         unsigned int i;
  33 #endif
  34         static const char * const freq[] = {"100", "125", "156.25", "212.5" };
  35
  36         printf("Board: %sDS, ", cpu->name);
  37         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  38                 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  39
  40         sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  41         sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  42
  43         if (sw < 0x8)
  44                 printf("vBank: %d\n", sw);
  45         else if (sw == 0x8)
  46                 puts("Promjet\n");
  47         else if (sw == 0x9)
  48                 puts("NAND\n");
  49         else
  50                 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
  51
  52         /* Display the actual SERDES reference clocks as configured by the
  53          * dip switches on the board.  Note that the SWx registers could
  54          * technically be set to force the reference clocks to match the
  55          * values that the SERDES expects (or vice versa).  For now, however,
  56          * we just display both values and hope the user notices when they
  57          * don't match.
  58          */
  59         puts("SERDES Reference Clocks: ");
  60 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
  61         || defined(CONFIG_P5040DS)
  62         sw = in_8(&PIXIS_SW(5));
  63         for (i = 0; i < 3; i++) {
  64                 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
  65
  66                 printf("Bank%u=%sMhz ", i+1, freq[clock]);
  67         }
  68 #ifdef CONFIG_P5040DS
  69         /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
  70         sw = in_8(&PIXIS_SW(9));
  71         printf("Bank4=%sMhz ", freq[sw & 3]);
  72 #endif
  73         puts("\n");
  74 #else
  75         sw = in_8(&PIXIS_SW(3));
  76         /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
  77         /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
  78         /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
  79         printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
  80         printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
  81         printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
  82 #endif
  83
  84         return 0;
  85 }
  86
  87 int board_early_init_f(void)
  88 {
  89         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  90
  91         /*
  92          * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
  93          * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
  94          * the noise introduced by these unterminated and unused clock pairs.
  95          */
  96         setbits_be32(&gur->ddrclkdr, 0x001B001B);
  97
  98         return 0;
  99 }
 100
 101 int board_early_init_r(void)
 102 {
 103         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 104         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 105
 106         /*
 107          * Remap Boot flash + PROMJET region to caching-inhibited
 108          * so that flash can be erased properly.
 109          */
 110
 111         /* Flush d-cache and invalidate i-cache of any FLASH data */
 112         flush_dcache();
 113         invalidate_icache();
 114
 115         if (flash_esel == -1) {
 116                 /* very unlikely unless something is messed up */
 117                 puts("Error: Could not find TLB for FLASH BASE\n");
 118                 flash_esel = 2; /* give our best effort to continue */
 119         } else {
 120                 /* invalidate existing TLB entry for flash + promjet */
 121                 disable_tlb(flash_esel);
 122         }
 123
 124         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 125                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 126                         0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 127
 128         set_liodns();
 129 #ifdef CONFIG_SYS_DPAA_QBMAN
 130         setup_portals();
 131 #endif
 132
 133         return 0;
 134 }
 135
 136 #define NUM_SRDS_BANKS  3
 137
 138 int misc_init_r(void)
 139 {
 140         serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 141         u32 actual[NUM_SRDS_BANKS];
 142         unsigned int i;
 143         u8 sw;
 144
 145 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
 146         || defined(CONFIG_P5040DS)
 147         sw = in_8(&PIXIS_SW(5));
 148         for (i = 0; i < 3; i++) {
 149                 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
 150                 switch (clock) {
 151                 case 0:
 152                         actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
 153                         break;
 154                 case 1:
 155                         actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
 156                         break;
 157                 case 2:
 158                         actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
 159                         break;
 160                 default:
 161                         printf("Warning: SDREFCLK%u switch setting of '11' is "
 162                                "unsupported\n", i + 1);
 163                         break;
 164                 }
 165         }
 166 #else
 167         /* Warn if the expected SERDES reference clocks don't match the
 168          * actual reference clocks.  This needs to be done after calling
 169          * p4080_erratum_serdes8(), since that function may modify the clocks.
 170          */
 171         sw = in_8(&PIXIS_SW(3));
 172         actual[0] = (sw & 0x40) ?
 173                 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
 174         actual[1] = (sw & 0x20) ?
 175                 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
 176         actual[2] = (sw & 0x10) ?
 177                 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
 178 #endif
 179
 180         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 181                 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
 182                 if (expected != actual[i]) {
 183                         printf("Warning: SERDES bank %u expects reference clock"
 184                                " %sMHz, but actual is %sMHz\n", i + 1,
 185                                serdes_clock_to_string(expected),
 186                                serdes_clock_to_string(actual[i]));
 187                 }
 188         }
 189
 190         return 0;
 191 }
 192
 193 void ft_board_setup(void *blob, bd_t *bd)
 194 {
 195         phys_addr_t base;
 196         phys_size_t size;
 197
 198         ft_cpu_setup(blob, bd);
 199
 200         base = getenv_bootm_low();
 201         size = getenv_bootm_size();
 202
 203         fdt_fixup_memory(blob, (u64)base, (u64)size);
 204
 205 #ifdef CONFIG_PCI
 206         pci_of_setup(blob, bd);
 207 #endif
 208
 209         fdt_fixup_liodn(blob);
 210         fdt_fixup_dr_usb(blob, bd);
 211
 212 #ifdef CONFIG_SYS_DPAA_FMAN
 213         fdt_fixup_fman_ethernet(blob);
 214         fdt_fixup_board_enet(blob);
 215 #endif
 216 }